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MC68HC681
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)TM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) MOTOROLA, 1996 All Rights Reserved.
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Applications and Technical Information
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TABLE OF CONTENTS
Paragraph Number Title Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Internal Control Logic ........................................................................... Timing Logic ......................................................................................... Interrupt Control Logic.......................................................................... Data Bus Buffer .................................................................................... Communication Channels A and B ...................................................... Input Port.............................................................................................. Output Port ........................................................................................... Section 2 Signal Descriptions 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.14.1 2.14.2 2.14.3 2.14.4 2.14.5 2.14.6 2.15 2.15.1 2.15.2 2.15.3 2.15.4 VCC and GND ....................................................................................... Crystal Input or External CLOCK (X1).................................................. Crystal Input (X2) ................................................................................. RESET (RESET) .................................................................................. Chip-Select (CS) .................................................................................. Read/Write (R/W) ................................................................................. Data Transfer Ackowledge (DTACK) ................................................... Register-Select Bus (RS1-RS4) .......................................................... Data Bus (D0-D7) ................................................................................ Interupt Request (IRQ) ......................................................................... Interupt Ackowledge (IACK) ................................................................. Channel A/B Transmitter Serial-Data Output (TxDA/TxDB)................. Channel A/B Receiver Serial-Data Input (RxDA/RxDB)....................... Parallel Inputs (IP0-IP5) ...................................................................... IP0 .............................................................................................. IP1 .............................................................................................. IP2 .............................................................................................. IP3 .............................................................................................. IP4 .............................................................................................. IP5 .............................................................................................. Parallel Outputs (OP0-OP7) ................................................................ OP0 ............................................................................................ OP1 ............................................................................................ OP2 ............................................................................................ OP3 ............................................................................................ 2-2 2-2 2-3 2-3 2-3 2-3 2-4 2-4 2-4 2-4 2-4 2-4 2-4 2-4 2-4 2-5 2-5 2-5 2-5 2-5 2-5 2-5 2-5 2-6 2-6 1-4 1-4 1-5 1-5 1-5 1-5 1-6 Page Number
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TABLE OF CONTENTS (Continued)
Paragraph Number 2.15.5 2.15.6 2.15.7 2.15.8 Title Page Number 2-6 2-6 2-6 2-6
OP4 ............................................................................................ OP5 ............................................................................................ OP6 ............................................................................................ OP7 ............................................................................................ Section 3 Operation
3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.5 3.5.1 3.5.2
Transmitter ........................................................................................... Receiver ............................................................................................... Looping Modes..................................................................................... Automatic-Echo Mode................................................................ Local-Loopback Mode................................................................ Remote-Loopback Mode............................................................ Multidrop Mode .................................................................................... Counter/Timer ...................................................................................... Counter Mode ............................................................................ Timer Mode ................................................................................ Section 4 Programming and Register Descriptions
3-1 3-2 3-4 3-5 3-5 3-5 3-5 3-6 3-6 3-7
4.1 4.2 4.3 4.3.1 4.3.1.1 4.3.1.2 4.3.1.3 4.3.1.4 4.3.1.5 4.3.1.6 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.3 4.3.4 4.3.5
Programming Descriptions................................................................... 4-1 Register Bit Formats ............................................................................ 4-6 Register Description........................................................................... 4-13 Channel A Mode Register 1 (MR1A)........................................ 4-13 Channel A Receiver Ready-To-Receive Control -- MR1A[7]. ..................................................... 4-13 Channel A Receiver-Interrupt Select - MR1A[6]........... 4-13 Channel A Error Mode Select - MR1A[5]...................... 4-13 Channel A Parity Mode Select - MR1A[4:3]. ................ 4-13 Channel A Parity Type Select - MR1A[2]. .................... 4-13 Channel A Bits-Per-Character Select - MR1A[1:0]........ 4-13 Channel A Mode Register 2 (MR2A)........................................ 4-14 Channel A Mode Select - MR2A[7:6]............................ 4-14 Channel A Transmitter Request-to-Send Control - MR2A[5]. ........................................................ 4-15 Channel A Clear-to-Send Control - MR2A[4]................ 4-16 Channel A Stop Bit Length Select - MR2A[3:2]. ........... 4-16 Channel B Mode Register 1 (MR1B)........................................ 4-16 Channel B Mode Register 2 (MR2B)........................................ 4-16 Channel A Clock-Select Register (CSRA) ............................... 4-16
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TABLE OF CONTENTS (Continued)
Paragraph Number 4.3.5.1 4.3.5.2 4.3.6 4.3.6.1 4.3.6.2 4.3.7 4.3.7.1 4.3.7.2 4.3.7.3 4.3.7.4 4.3.8 4.3.9 4.3.9.1 4.3.9.2 4.3.9.3 4.3.9.4 4.3.9.5 4.3.9.6 4.3.9.7 4.3.9.8 4.3.10 4.3.11 4.3.11.1 4.3.11.2 4.3.11.3 4.3.11.4 4.3.11.5 4.3.11.6 4.3.12 4.3.13 4.3.13.1 4.3.13.2 4.3.13.3 4.3.14 4.3.14.1 4.3.14.2 4.3.15 4.3.15.1 4.3.15.2 4.3.15.3 Title Page Number
Channel A Receiver Clock Select - CSRA[7:4]............. 4-16 Channel A Transmitter Clock Select - CSRA[3:0]......... 4-16 Channel B Clock-Select Register (CSRB)................................ 4-17 Channel B Receiver Clock Select - CSRB[7:4]............. 4-17 Channel B Transmitter Clock Select - CSRB[3:0]......... 4-17 Channel A Command Register (CRA)...................................... 4-17 CRA[7]. ......................................................................... 4-17 Channel A Miscellaneous Commands - CRA[6:4]. ....... 4-17 Channel A Transmitter Commands - CRA[3:2]............. 4-18 Channel A Receiver Commands - CRA[1:0]................. 4-18 Channel B Command Register (CRB)...................................... 4-19 Channel A Status Register (SRA) ............................................ 4-19 Channel A Received Break - SRA[7]. ........................... 4-19 Channel A Framing Error - SRA[6]. .............................. 4-19 Channel A Parity Error - SRA[5]. .................................. 4-19 Channel A Overrun Error - SRA[4]. .............................. 4-19 Channel A Transmitter Empty - SRA[3]. ....................... 4-19 Channel A Transmitter Ready - SRA[2]........................ 4-20 Channel A FIFO Full - SRA[1]. ..................................... 4-20 Channel A Receiver Ready - SRA[0]............................ 4-20 Channel B Status Register (SRB) ............................................ 4-20 Output Port Configuration Register (OPCR) ............................ 4-20 OP7 Output Select - OPCR[7]. ..................................... 4-20 OP6 Output Select - OPCR[6]. ..................................... 4-20 OP5 Output Select - OPCR[5]. ..................................... 4-20 OP4 Output Select - OPCR[4]. ..................................... 4-20 OP3 Output Select - OPCR[3:2]. .................................. 4-21 OP2 Output Select - OPCR[1:0]. .................................. 4-21 Output Port Register - OPR[7:0]............................................... 4-21 Auxiliary Control Register (ACR).............................................. 4-21 Baud-Rate Generator Set Select - ACR[7]. .................. 4-21 Counter/Timer Mode and Clock Source Select -- ACR[6:4]. .......................................................4-22 IP3, IP2, IP1, and IP0 Change-of-State Interrupt Enable -- ACR[3:0]. .....................................................4-22 Input Port Change Register (IPCR).......................................... 4-22 IP3, IP2, IP1, and IP0 Change of State - IPCR[7:4]. .... 4-22 IP31 IP2F IP1, and IP0 Current State -- IPCR[3:0]. .... 4-22 Interrupt Status Register (ISR) ................................................. 4-22 Input Port Change Status - ISR[7]. .............................. 4-23 Channel B Change in Break -- ISR[6].......................... 4-23 Channel B Receiver Ready or FIFO Full -- ISR[5]....... 4-23
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TABLE OF CONTENTS (Continued)
Paragraph Number 4.3.15.4 4.3.15.5 4.3.15.6 4.3.15.7 4.3.15.8 4.3.16 4.3.17 4.3.18 4.3.19 Title Page Number 4-23 4-23 4-23 4-23 4-23 4-23 4-24 4-24 4-24
Channel B Transmitter Ready -- ISR[4]....................... Counter/Timer Ready -- ISR[3].................................... Channel A Change in Break -- ISR[2]. ........................ Channel A Receiver Ready or FIFO Full -- ISR[1]. ..... Channel A Transmitter Ready -- ISR[0]....................... Interrupt Mask Register (IMR).................................................. Count Registers (CUR and CLR) ............................................. Counter/Timer Preload Registers (CTUR and CTLR).............. Interrupt Vector Register (IVR)................................................. Section 5 Electrical Specifications
5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9
Absolute Maximum Ratings ................................................................. 5-1 Thermal Characteristics ....................................................................... 5-1 Power Considerations .......................................................................... 5-1 DC Electrical Characteristics................................................................ 5-2 AC Electrical Characteristics................................................................ 5-3 Clock Timing .............................................................................. 5-3 RESET Timing ........................................................................... 5-4 Read and Write Bus Cycle Timing ............................................. 5-4 Interrupt Bus Cycle Timing......................................................... 5-5 Port Timing................................................................................. 5-7 Interrupt Reset Timing................................................................ 5-8 Transmitter Timing ..................................................................... 5-8 Receiver Timing ......................................................................... 5-9 Transmit And Receive Operation ............................................. 5-10 Section 6 Mechanical Data and Ordering Information
6.1 6.2 6.3 6.4 6.5 6.6
Pin Assignments .................................................................................. 6-1 Ordering Information ............................................................................ 6-1 Package Dimensions ........................................................................... 6-2 Pin Assignment-40 Pin Dual-In-Line Plastic Package.......................... 6-3 Ordering Information ............................................................................. 6-3 Package Dimensions-40 Pin Dual-In-Line Package............................. 6-4
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Paragraph Number Title Appendix A MC68HC2681 A.1 A.1.1 A.1.2 A.2 A.2.1 A.2.2 A.2.3 A.2.4 A.2.5 A.2.6 A.3 A.4 A.4.1 A.4.2 A.4.3 A.4.4 A.4.4.1 A.4.4.2 A.4.4.3 A.4.4.4 A.4.4.5 A.4.4.6 A.4.4.7 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.5.5 A.5.6 Introduction ......................................................................................... A-1 Interrupt Control Logic.............................................................. A-1 Input Port.................................................................................. A-1 Signal Description ................................................................................ A-1 Reset (RESET)......................................................................... A-4 Chip-Select (CS) ...................................................................... A-4 Write Strobe (W)....................................................................... A-4 Read Strobe (R) ....................................................................... A-4 Parallel Input 6 (IP6)................................................................. A-4 Parallel Input 2 (IP2)................................................................. A-4 Programming and Register Description .............................................. A-4 Electrical Specifications ...................................................................... A-6 Absolute Maximum Ratings...................................................... A-6 Thermal Characteristics ........................................................... A-6 DC Electrical Characteristics.................................................... A-6 AC Electrical Characteristics .................................................... A-7 Clock Timing ................................................................. A-7 RESET Timing .............................................................. A-8 Bus Timing..................................................................... A-8 Port Timing ................................................................... A-9 Interrupt Reset Timing ................................................. A-9 Transmitter Timing....................................................... A-10 Receiver Timing.......................................................... A-10 Mechanical Data and Ordering Information ....................................... A-14 Pin Assignment--44 Pin Plastic Leaded Chip Carrier.............. A-14 FN Suffix Ordering Information................................................. A-14 FN Suffix Packaging Dimensions ............................................. A-15 Pin Assignment--40 Pin Dual-In Line Plastic Package............ A-16 P Suffix Ordering Information ................................................... A-16 Packaging Dimensions--Plastic............................................... A-17 Page Number
Index
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TABLE OF CONTENTS (Continued)
Paragraph Number Title Page Number
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LIST OF TABLES
Table Number 2-1. 4-1. 4-2. 4-3. 4-4. 4-5. A-1. A-2. Title Page Number
Signal Summary ..............................................................................................2-1 Register Addressing and Address-Triggered Commands ...............................4-3 Programming of Input Port Functions .............................................................4-3 Programming of Output Port Functions ...........................................................4-4 Selection of Clock Sources for the Counter/Timer ..........................................4-5 Baud-Rate Generator Characteristics Crystal or Clock = 3.6864 MHz .........4-22 MC68HC2681 Signal Summary ..................................................................... A-3 MC68HC2681 Register Addressing and Address-Triggered Commands ...... A-5
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LIST OF ILLUSTRATIONS
Figure Number 1-1. 4-1. 5-1. 5-2. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. 5-10. 5-11. 5-12. A-1. A-2. A-3. A-4. A-5. A-6. A-7. A-8. A-9. A-10. A-11. Title Page Number
68HC681Block Diagram ...................................................................................1-2 Programming Block Diagram ...........................................................................4-2 Clock Timing ....................................................................................................5-3 RESET Timing .................................................................................................5-4 Read Cycle Bus Timing ....................................................................................5-6 Write Cycle Bus Timing ....................................................................................5-6 Interrupt Cycle Bus Timing ...............................................................................5-7 Port Timing .......................................................................................................5-7 Interrupt Reset Timing ......................................................................................5-8 Transmitter Timing ...........................................................................................5-8 Receiver Timing ...............................................................................................5-9 Transmitter Operation ....................................................................................5-10 Receiver Operation ........................................................................................5-11 Wake-Up Mode Operation .............................................................................5-12 MC68HC2681 Block Diagram ......................................................................... A-2 Clock Timing ................................................................................................... A-7 RESET Timing ................................................................................................ A-8 Bus Timing ...................................................................................................... A-8 Port Timing ...................................................................................................... A-9 Interrupt Reset Timing .................................................................................... A-9 Transmitter Timing ........................................................................................ A-10 Receiver Timing ............................................................................................ A-10 Transmitter Operation ................................................................................... A-11 Receiver Operation ....................................................................................... A-12 Wake-Up Mode Operation ............................................................................ A-13
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1
SECTION 1 INTRODUCTION
The MC68HC681 dual universal asynchronous receiver/transmitter (DUART) is part of the M68000 Family of peripherals and directly interfaces to the MC68000 processor via an asynchronous bus structure. The MC68HC681 consists of these major sections: * Internal Control Logic * Timing Logic * Interrupt Control Logic * Bidirectional 8-bit Data Bus Buffer * Two Independent Communication Channels (A and B) * 6-bit Parallel Input Port * 8-bit Parallel Output Port The MC68HC2681 dual asynchronous receiver/transmitter (DUART) is functionally equivalent to the MC68HC681 with some minor differences. The description of the MC68HC681 applies to the MC68HC2681 except for the areas described in Appendix A MC68HC2681 located in the back of this document. Figure 1-1 is a basic block diagram of the MC68HC681 and should be referred to during the discussion of its features, which include the following: * M68000 Bus Compatible * Two Independent Full-Duplex Asynchronous Receiver/Transmitter Channels * Maximum Data Transfer Rate: -- 1X -- 1 Mbits/second -- 16X -- 250 kbits/second * Quadruple-Buffered Receiver Data Registers * Double-Buffered Transmitter Data Registers * Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable From: -- 18 Fixed Rates: 50 to 38.4k Baud -- One User Defined Rate Derived from a Programmable Timer/Counter -- External 1X Clock or 16X Clock
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1-1
Introduction
1
DTACK R/W CS RESET RS4-RS1 INTERNAL CONTROL LOGIC
TIMING LOGIC X1 X2
CSRA CHANNEL A CLOCK SELECT REG CSRB CHANNEL B CLOCK SELECT REG ACR W W
AUXILIARY CONTROL REG (4 BITS) W COUNTER/TIMER LOWER REGISTER (LEAST SIGNIF 8 BITS) W*
COUNTER/TIMER UPPER REGISTER (MOST SIGNIF 8 BITS) W*
* Current Count in Counter Mode may be Read
INTERNAL DATA BUS
PROCESSOR INTERFACE
EXTERNAL INTERFACE CHANNEL A
CRA MR1A MR2A SRA TBA THRA COMMAND REGISTER MODE REGISTER 1 MODE REGISTER 2 STATUS REGISTER TRANSMIT HOLDING REG TRANSMIT SHIFT REG RHRA RECEIVE HOLDING REG (3) RHRA (2) RHRA (1) RECEIVE SHIFT REGISTER R W R/W R/W R W
TxDA
D7-D0
DATA BUS BUFFER RBA
FIFO RxDA
CHANNEL B
CRB MR1B MR2B SRB TBB THRB COMMAND REGISTER MODE REGISTER 1 MODE REGISTER 2 STATUS REGISTER TRANSMIT HOLDING REG TRANSMIT SHIFT REGISTER RHRB R W R/W RBB W RECEIVE HOLDING REG (3) RHRB (2) RHRB (1) RECEIVE SHIFT REGISTER R W R/W R/W R W
TxDB FIFO RxDB
INTERRUPT CONTROL LOGIC
IRQ IACK
IMR
INTERRUPT MASK REG
ISR INTERRUPT STATUS REG ACR * AUX CONTROL REG (4 BITS) Same ACR as in Input Port * IVR INTERRUPT VECTOR REG
INPUT PORT
IPCR INPUT PORT CHANGE REG R W R
IP5-IP0
AUX CONTROL REG (4 BITS) ACR * * Same ACR as in Interrupt Control Logic ACR INPUT PORT (6 BITS)
VCC GND
OPCR OPR
OUTPUT PORT
OUTPUT PORT CONFIG REG OUTPUT PORT REG (8 BITS) W W
OP7-OP0
Figure 1-1. MC68HC681 Block Diagram
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Introduction
* Programmable Data Format -- Five to eight data bits -- Odd, Even, force parity, or no parity -- One, one and one-half, or two stop bits * Programmable Channel Modes -- -- -- -- Normal (full duplex) Automatic echo Local loopback Remote loopback
1
* Automatic Wake-up Mode for Multidrop Applications * Multifunction 6-Bit Input Port -- Clock or control input functions -- Change-of-state detection on four inputs * Multifunction 8-Bit Output Port -- Individual bit set/reset capability -- Status/Interrupt signal programmable outputs * Multifunction 16-Bit Programmable Counter/Timer * Versatile Interrupt System -- Single interrupt output with eight maskable interrupting conditions -- Interrupt vector output on interrupt acknowledge -- Programmable output port can be configured to provide as many as six separate wire-ORable interrupt outputs * Parity, Framing, and Overrun Error Detection * False-Start Bit Detection * Line-Break Detection and Generation * Break Detection starting in the Middle of a Character * Start-End Break Interrupt/Status * On-Chip Crystal Oscillator * TTL Compatible * Single +5V Power Supply
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Introduction
1
1.1 INTERNAL CONTROL LOGIC
The internal control logic receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. The internal control logic allows access to the registers within the DUART and performs various commands by decoding the four register-select lines (RS1 through RS4). Besides the four register-select lines, there are three other inputs to the internal control logic from the CPU: read/write (R/W), which allows read and write transfers between the CPU and DUART via the data bus buffer; chip-select (CS), which is the DUART chip-select; and reset (RESET), which initializes or resets the DUART. The data transfer acknowledge (DTACK) signal, which is asserted during read, write, or interrupt-acknowledge cycles, is the internal control logic output. The DTACK signal indicates to the CPU that data has been latched on a CPU write cycle or that valid data is present on the data bus during a CPU read cycle or interrupt-acknowledge (IACK) cycle.
1.2 TIMING LOGIC
The timing logic consists of a crystal oscillator, a baud-rate generator (BRG), a programmable 16-bit counter/timer (C/T), and four clock selectors. The crystal oscillator operates directly from a 3.6864 MHz crystal connected across the X1 and X2 inputs or from an external clock of the appropriate frequency connected to X1. The X1 clock serves as the basic timing reference for the baud-rate generator, the C/T, and other internal circuits. The part can operate without an X1 clock but with the following restrictions: * The X1 input must be connected to GND or VCC * The receiver(s) and transmitter(s), if used, must not be programmed to select any of the 18 standard rates generated by the BRG * The counter/timer, if used, must not be programmed to the X1 or X1/16 selection * The change-detect on IP0-IP3 will not operate * DTACK will not be generated on any bus cycle The baud-rate generator operates from the X1 clock input and can generate 18 commonly used data communication baud rates ranging from 50 to 38.4k by producing internal clock outputs at 16 times the actual baud rate. The C/T can produce a 16X clock for other baud rates by counting down its programmed clock source. Other baud rates can also be derived by connecting 16X or 1X clocks to certain input port pins that have alternate functions as receiver or transmitter clock inputs. Four clock selectors allow the independent selection of any of these baud rates for each receiver and transmitter. Customers can program the 16bit C/T within the DUART to use one of several clock sources as its input. The output of the C/T is available to the internal clock selectors and can also be programmed to appear at parallel output OP3. In the timer mode, the C/T acts as a programmable divider and can generate a square-wave output at OP3. In the counter mode, the C/T can be started and stopped under program control. When stopped, the CPU can read its contents. The counter counts down the number of pulses stored in the concatenation of the C/T upper register and C/T lower register and produces an interrupt. This is a system-oriented feature that can be used to record timeouts when implementing various application protocols.
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1.3 INTERRUPT CONTROL LOGIC
The following registers are associated with the interrupt control logic: * Interrupt Mask Register (IMR) * Interrupt Status Register (ISR) * Auxiliary Control Register (ACR) * Interrupt Vector Register (IVR) Refer to Section 4 Programming and Register Descriptions for more complete information on these registers. A single active-low interrupt output (IRQ) can notify the processor that any of eight internal events has occurred. These eight events are described in the discussion of the interrupt status register (ISR) in Section 4 Programming and Register Descriptions. Customers can program the interrupt mask register (IMR) to allow only certain conditions to cause IRQ to be asserted while the CPU can read the ISR to determine all currently active interrupting conditions. When an active-low interrupt acknowledge signal (IACK) from the processor is asserted while the DUART has an interrupt pending, the DUART will place the contents of the interrupt vector register (IVR) on the data bus and assert the data transfer acknowledge signal (DTACK). If the DUART has no pending interrupt, it ignores IACK cycles. In addition, customers can program the parallel outputs OP3 through OP7 to provide discrete interrupt outputs for the transmitters, the receivers, and the C/T.
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1.4 DATA BUS BUFFER
The data bus buffer provides the interface between the external and internal data buses. It is controlled by the internal control logic to allow read and write data transfer operations to occur between the controlling CPU and DUART by way of the eight parallel data lines (DO through D7).
1.5 COMMUNICATION CHANNELS A AND B
Each communication channel comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and each transmitter can be selected independently from the baud-rate generator, the C/T, or from an external clock. The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, and outputs a composite serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), or break condition, and transfers an assembled character to the CPU during read operations.
1.6 INPUT PORT
The CPU reads the inputs to this 6-bit port (IP0 through IP5). High or low inputs to the input port result in the CPU reading a logic one or logic zero, respectively; that is, there is no inversion of the logic level. Each input port bit also has an alternate control function capability. The alternate functions can be enabled/disabled on a bit-by-bit basis.
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Four change-of-state detectors are associated with inputs IP0, IP1, IP2, and IP3. If a highto-low or low-to-high transition occurs on any of these inputs and the new level is stable for more than 25 to 50 microseconds (best-to-worst case times), the corresponding bit in the input port change register (IPCR) will be set. The sampling clock of the change detectors is the X1/96 tap of the baud-rate generator (the 2400 baud tap), which is 38.4kHz if X1 is 3.6864MHz. A new input level must be sampled on two consecutive sample clocks to produce a change detect. Also, customers can program the DUART to allow a change of state to generate an interrupt to the CPU. The IPCR bits are cleared when the CPU reads the register.
1.7 OUTPUT PORT
This 8-bit multipurpose output port can be used as a general-purpose output port. Associated with the output port is an output port register (OPR). All bits of the OPR can be individually set and reset. A bit is set by performing a write operation at the appropriate address with the accompanying data specifying the bits to be set (one equals set and zero equals no change). Similarly, a bit is reset by performing a write operation at another address with the accompanying data specifying the bits to be reset (one equals reset and zero equals no change). The OPR stores data that is to be output at the output port pins. Unlike the input port, if a particular bit of the OPR is set to a logic one or logic zero, the output pin will be at a low or high level, respectively. Thus, a logic inversion occurs internal to the DUART with respect to this register. The outputs are complements of the data contained in the OPR. Table 4-1 and Section 4 Programming and Register Descriptions provide more information on the address location of the output port register and setting and resetting bits of this register. Besides general-purpose outputs, the outputs can be individually assigned specific auxiliary functions serving the communication channels. The assignment is accomplished by appropriately programming the channel A and B mode registers (MR1A, MR1B, MR2A, and MR2B) and the output port configuration register (OPCR). Section 4 Programming and Register Descriptions provides more information on the mode registers and the OPCR.
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SECTION 2 SIGNAL DESCRIPTIONS
This section briefly describes the input and output signals. Table 2-1 provides a quick reference for determining a signal's pin number, its use as an input or output, whether it is active high or low, and the section that contains more information about its operation. NOTE The terms assertion and negation will be used extensively to avoid confusion when dealing with a mixture of "active low" and "active high" signals. The term assert or assertion indicates that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.
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Table 2-1. Signal Summary
PIN NO. SIGNAL NAME Power Supply (5 V) Ground Crystal Input or External Clock Crystal Output Reset Chip Select Read/Write Data Transfer Acknowledge Register-Select Bus Bit 4 Register-Select Bus Bit 3 Register-Select Bus Bit 2 Register-Select Bus Bit 1 Bidirectional-Data Bus Bit 7 Bidirectional-Data Bus Bit 6 Bidirectional-Data Bus Bit 5 Bidirectional-Data Bus Bit 4 Bidirectional-Data Bus Bit 3 MNEMONIC P PKG. VCC GND X1 X2 RESET CS R/W DTACK RS4 RS3 RS2 RS1 D7 D6 D5 D4 D3 40 20 32 33 34 35 8 9 6 5 3 1 19 22 18 23 17 FN PKG. 44 22 36 37 38 39 9 10 7 6 4 2 21 25 20 26 19 In In In Out In In In Out1 In In In In In/Out In/Out In/Out In/Out In/Out IN/OUT ACTIVE STATE High Low -- -- Low Low High/Low Low High High High High High High High High High REFER TO PARA. NO. 2.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8 2.8 2.8 2.9 2.9 2.9 2.9 2.9
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Table 2-1. Signal Summary (Continued)
PIN NO. SIGNAL NAME Bidirectional-Data Bus Bit 2 MNEMONIC P PKG. D2 D1 D0 IRQ IACK TxDA RxDA TxDB RxDB IP5 IP4 IP3 IP2 IP1 IP0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 24 16 25 21 37 30 31 11 10 38 39 2 36 4 7 15 26 14 27 13 28 12 29 FN PKG. 27 18 28 24 41 33 35 13 11 42 43 3 40 5 8 17 29 16 30 15 31 14 32 In/Out In/Out In/Out Out 1 In Out In Out In In In In In In In Out 2 Out 2 Out 2 Out
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IN/OUT
ACTIVE STATE High High High Low Low -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
REFER TO PARA. NO. 2.9 2.9 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16.1 2.16.2 2.16.3 2.16.4 2.16.5 2.16.6 2.17.1 2.17.2 2.17.3 2.17.4 2.17.5 2.17.6 2.17.7 2.17.8
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Bidirectional-Data Bus Bit 1 Bidirectional-Data Bus Bit 0 (Least-Significant Bit) Interrupt Request Interrupt Acknowledge Channel A Transmitter Serial Data Channel A Receiver Serial Data Channel B Transmitter Serial Data Channel B Receiver Serial Data Parallel Input 5 Parallel Input 4 Parallel Input 3 Parallel Input 2 Parallel Input 1 Parallel Input 0 Parallel Output 7 Parallel Output 6 Parallel Output 5 Parallel Output 4 Parallel Output 3 Parallel Output 2 Parallel Output 1 Parallel Output 0 NOTES:
Out 2 Out Out Out
1. 2.
Requires a pullup resistor May require a pullup resistor, depending on its programmed function.
2.1 VCC AND GND
Power is supplied to the DUART using these two signals. VCC is power ( + 5 volts) and GND is the ground connection.
2.2 CRYSTAL INPUT OR EXTERNAL CLOCK (X1)
This input is one of two connections to a crystal or a connection to an external CMOS-level clock. If a crystal is used, a capacitor of approximately 10 to 15 picofarads should be connected from this pin to ground.
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2.3 CRYSTAL INPUT (X2)
This input is an additional connection to a crystal (see Section 2 Signal Descriptions). If an external CMOS-level clock is used, this pin must be left open. If a crystal is used, a capacitor of approximately 10 to 15 picofarads should be connected from this pin to ground.
2.4 RESET (RESET)
The DUART can be reset by asserting the RESET signal or by programming the appropriate command register. A hardware reset (assertion of RESET) clears the following registers: * Status registers A and B (SRA and SRB) * Interrupt mask register (IMR) * Interrupt status register (ISR) * Output port register (OPR) * Output port configuration register (OPCR) RESET performs the following operations: * Initializes the interrupt vector register (IVR) to 0F16 * Places parallel outputs OP0 through OP7 in the high state * Places the counter/timer in timer mode * Places channels A and B in the inactive state with the transmitter serial-data outputs (TxDA and TxDB) in the mark (high) state. Software resets are not as encompassing and are achieved by appropriately programming the channel A and/or B command registers. Reset commands can be programmed through the command register to reset the receiver, transmitter, error status, or break-change interrupts for each channel. Refer to Section 4 Programming and Register Descriptions for more information.
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2.5 CHIP-SELECT (CS)
This active-low input signal, when low, enables data transfers between the CPU and DUART on the data lines (D0 through D7). These data transfers are controlled by read/write (R/W) and the register-select inputs (RS1 through RS4). When chip-select is high, the D0 through D7 data lines are placed in the high-impedance state.
2.6 READ/WRITE (R/W)
When high, this input indicates a read cycle; when low, it indicates a write cycle. Assertion of the chip-select input initiates a cycle.
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2.7 DATA TRANSFER ACKOWLEDGE (DTACK)
This three-state active low output is asserted in read, write, or interrupt-acknowledge (IACK) cycles to indicate the proper transfer of data between the CPU and DUART. If there is no pending interrupt on an IACK cycle, DTACK is not asserted. DTACK is an "active rescind" signal: at the end of a transfer, it drives high momentarily, then is three-stated so that it can be wire-ANDed with other DTACK sources, like an open-drain signal.
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2.8 REGISTER-SELECT BUS (RS1-RS4)
The register-select bus lines during read/write operations select the DUART internal registers, ports, or commands.
2.9 DATA BUS (D0-D7)
These bidirectional three-state data lines transfer commands, data, and status between the CPU and DUART. D0 is the least-significant bit.
2.10 INTERUPT REQUEST (IRQ)
This active-low, open-drain output signals the CPU that one or more of the eight maskable interrupting conditions are true.
2.11 INTERUPT ACKOWLEDGE (IACK)
This active-low input indicates an interrupt-acknowledge cycle. If there is an interrupt pending (IRQ asserted) and this pin is asserted, the DUART responds by placing the interrupt vector on the data bus and then asserting DTACK. If there is no interrupt pending (IRQ negated), the DUART ignores this pin.
2.12 CHANNEL A/B TRANSMITTER SERIAL-DATA OUTPUT (TxDA/TxDB)
The independent transmitter serial-data outputs for channel A and B transmit the least-significant bit first. The output is held high (mark condition) when its associated transmitter is disabled, idle, or operating in the local loopback mode. (``Mark'' is high and ``space'' is low.) Data is shifted out from this pin on the falling edge of the programmed clock source.
2.13 CHANNEL A/B RECEIVER SERIAL-DATA INPUT (RxDA/RxDB)
The independent receiver serial-data inputs for channel A and B receive the least-significant bit first. Data on these pins is sampled on the rising edge of the programmed clock source.
2.14 PARALLEL INPUTS (IP0-IP5)
The parallel inputs can be used as general-purpose inputs. However, each pin also has an alternate function(s) described below.
2.14.1 IP0
This input can be used as the channel A clear-to-send active-low input (CTSA). A change-ofstate detector is also associated with this input.
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2.14.2 IP1
This input can be used as the channel B clear-to-send active-low input (CTSB). A change-ofstate detector is also associated with this input.
2.14.3 IP2
This input can be used as the channel B receiver external clock input (RxCB), or the counter/timer external clock input. When this input functions as the external clock to the receiver, the received data is sampled on the rising edge of the clock. A change-of-state detector is also associated with this input.
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2.14.4 IP3
This input can serve as the channel A transmitter external clock input (TxCA). When this input functions as the external clock to the transmitter, the transmitted data is clocked on the falling edge of the clock. A change-of-state detector is also associated with this input.
2.14.5 IP4
This input can be used as the channel A receiver external clock input (RxCA). When this input functions as the external clock to the receiver, the received data is sampled on the rising edge of the clock.
2.14.6 IP5
This input can serve as the channel B transmitter external clock (TxCB). When this input is used as the external clock to the transmitter, the transmitted data is clocked on the falling edge of the clock.
2.15 PARALLEL OUTPUTS (OP0-OP7)
The parallel outputs can be used as general-purpose outputs; however, each pin also has an alternate function(s), described below.
2.15.1 OP0
This output can function as the channel A transmitter active-low request-to-send (RTSA) output, or as the channel A receiver active-low ready-to-receive (RTRA) output. When used for RTSA, it is automatically negated by the transmitter. When used for RTRA, the receiver automatically negates and reasserts OP0.
2.15.2 OP1
This output can serve as the channel B transmitter active-low request-to-send (RTSB) output, or as the channel B receiver active-low ready-to-receive (RTRB) output. When used for RTSB, the transmitter automatically negates OP1 by the transmitter. When used for RTRB, the receiver automatically negates and reasserts OP1.
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2.15.3 OP2
This output can be used as the channel A transmitter 1X-clock or 16X-clock output or the channel A receiver 1X-clock output.
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2.15.4 OP3
This output can function as the open-drain active-low counter-ready output, the open-drain timer output, the channel B transmitter 1X-clock output, or the channel B receiver 1X-clock output.
2.15.5 OP4
This output can serve as the channel A open-drain active-low receiver-ready or buffer-full interrupt outputs (RxRDYA/FFULLA) by appropriately programming bit 6 of mode register 1A.
2.15.6 OP5
This output can be used as the channel B open-drain active-low receiver-ready or buffer-full interrupt outputs (RxRDYB/FFULLB) by appropriately programming bit 6 of mode register 1B.
2.15.7 OP6
This output can function as the channel A open-drain active-low transmitter-ready interrupt output (TxRDYA).
2.15.8 OP7
This output can serve as the channel B open-drain active-low transmitter-ready interrupt output (TxRDYB).
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SECTION 3 OPERATION
3.1 TRANSMITTER
The channel A and B transmitters are enabled for data transmission through their respective command registers (refer to Section 4 Programming and Register Descriptions). The DUART signals the CPU it is ready to accept a character by setting the transmitter-ready bit in the channel's status register. Customers can program this condition to generate an interrupt request on the IRQ output, an interrupt request for channel A's transmitter on parallel output OP6, or for channel B's transmitter on parallel output OP7. When a character is loaded into the transmit buffer (TB), the above conditions for the respective channel are negated. Data is transferred from the transmit holding register to the transmit shift register when the shift register is idle or has completed transmission of the previous character. The transmitter ready conditions are then re-asserted, providing one full character time of buffering. Characters cannot be loaded into the transmit buffer while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the transmitter serial-data output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least-significant bit is sent first. Data is shifted out the transmit serial data output pin on the failing edge of the programmed clock source. After the transmission of the stop bits, if a new character is not available in the transmit holding register the transmitter serial-data output remains high and the transmitter-empty bit in the status register (SRA and SRB) will be set to a one. Transmission resumes and the transmitter-empty bit is cleared when the CPU loads a new character into the transmit buffer (TBA or TBB). If the transmitter receives a disable command, it will continue operating until the character in the transmit shift register is completely sent out. Another character in the holding register is not sent but is not discarded; it will be sent when the transmitter is re-enabled. The transmitter can be reset through a software command (refer to Section 2.4 RESET). If it is reset, operation ceases immediately and must be enabled through the command register before resuming operation. Reset also discards any character in the holding register. If clear-to-send (CTS) operation is enabled, the CTS input (alternate function of IP0 or IP1) must be low in order for the character to be transmitted. If it goes high in the middle of a transmission, the character in the shift register is transmitted and TxD then remains in the marking state until CTS again goes low. The transmitter can also be forced to send a continuous low condition by issuing a send-break command. The state of CTS is ignored by the transmitter when it is to send a break.
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A send-break is deferred as long as the transmitter has characters to send, but if normal character transmission is inhibited by CTS, the send-break will proceed. The send-break must be terminated by a stop-break, disable, or reset before normal character transmission can resume. Customers can program the transmitter to automatically negate the request-to-send (RTS) output (alternate function of OP0 and OP1) on completion of a message transmission. If the transmitter is programmed to operate in this manner, the RTS output must be manually asserted before each message is transmitted. If OP0 (or OP1) is programmed in automatic RTS mode, the RTS output will be automatically negated when the transmitter is disabled and the transmit-shift register and holding register are both empty. In automatic RTS mode, a character in the holding register is not held back by a disable, but no more characters can be written to the holding register after the transmitter is disabled.
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3.2 RECEIVER
The channel A and B receivers are enabled for data reception through the respective channel's command register. The channel's receiver looks for the high-to-low (mark-tospace) transition of a start bit on the receiver serial-data input pin. If operating in 16X clock mode, the serial input data is re-sampled on the next 7 clocks. If the receiver serial data is sampled high, the start bit is invalid and the search for a valid start bit begins again. If receiver serial data is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity bit (if any) have been assembled and one stop bit has been detected. Data on the receiver serial data input pin is sampled on the rising edge of the programmed clock source. During this process, the least-significant bit is received first. The data is then transferred to a receive holding register (RHR) and the receiver-ready bit in the status register (SRA or SRB) is set to a one (see Figure 3-1). This condition can be programmed to generate an interrupt request on the IRQ output, an interrupt request for channel A's receiver on parallel output OP4, or an interrupt request for channel B's receiver on parallel output OP5. If the character length is less than eight bits, the most significant unused bits in the receive holding register (RHR) are set to zero. If the stop bit is sampled as a 1, the receiver will immediately look for the next start bit. However, if the stop bit is sampled as a 0, either a framing error or a received break has occurred. If the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing error; the damaged character is transferred to a holding register with the framing error flag set. If the receiver serial data remains low for one-half of the bit period after the stop bit was sampled, the receiver operates as if a new start bit transition has been detected. If the stop bit is 0 and the data and parity (if any) are also all zero, it is a break. A character consisting of all zeros will be loaded into a receive holding register (RHR) with the received-break bit (but not the framing error bit) set to a one. The receiver serial-data input must return to a high condition for at least one-half bit time before a search for the next start bit begins.
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The receiver can detect a break that starts in the middle of a character provided the break persists completely through the next character time or longer. When the break begins in the middle of a character, the receiver will place the damaged character in a holding register with the framing error bit set. Then, provided the break persists through the next character time, the receiver will also place an all-zero character in the next holding register with the received-break bit set. The parity error, framing error, overrun error, and received-break conditions (if any) set error and break flags in the status register at the received character boundary and are valid only when the receiver-ready bit (RxRDY) in the status register is set. A first-in first-out (FIFO) stack is used in each channel's receive buffer logic and consists of three receive holding registers. The receiver buffer (RBA or RBB) is composed of the FIFO and a receive shift register connected to the receiver serial-data input. Data is assembled in the shift register and loaded into the top-most empty FIFO receive holding register position. Thus, data flowing from the receiver to the CPU is quadruply buffered. The receiver-ready bit in the status register (SRA or SRB) is set whenever one or more characters are available to be read. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are "popped" and new data can be added at the bottom of the stack by the receive shift register. The FIFO-full status bit is set if all three stack positions are filled with data. Either the receiver-ready or the FIFO-full status bits can be selected to cause an interrupt. In addition to the data byte, three status bits (parity error, framing error, and received break) are appended to each data character in the FIFO (overrun is not). By programming the error-mode control bit in the channel's mode register, status can be provided for "character" or "block" modes. In the "character" mode, the status register (SRA or SRB) is updated on a character-bycharacter basis and applies only to the character at the top of the FIFO. Thus, the status must be read before the character is read. Reading the character pops it and its error flags off the FIFO. In the "block" mode, the status provided in the status register for the parity error, framing error, and received-break conditions is the logical OR of these respective bits for all characters coming to the top of the FIFO stack since the last reset error command was issued. That is, beginning at the last reset-error command issued, a continuous logical-OR function of corresponding status bits is produced in the status register as each character comes to the top of the FIFO stack. The block mode is useful in applications requiring the exchange of blocks of information where the software overhead of checking each character's error flags cannot be tolerated. In this mode, entire messages can be received and only one data integrity check is performed at the end of each message. Although data reception in this manner has speed advantages, there are also disadvantages. Because each character is not individually checked for error conditions by the software, if an error occurs within a message the error will not be recognized until the final check is performed. Also, there is no indication of which character(s) is in error within the message.
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The block mode can only be used if either (or both) of two conditions can be guaranteed: 1. The length of the block is known before the last character of the block is read, so that the block error status can be read and cleared before reading the last character; 2. There will never be another character already present in the FIFO until the last character of the message is read (leaving the FIFO empty), the status is read, and a reset error command is issued. Otherwise, errors in the first character of the next block could be reported erroneously on the current block, or they could be prematurely cleared and not reported in the error status of the next block. In either mode, reading the status register (SR) does not affect the FIFO. The FIFO is "popped" only when the receive buffer (RBA or RBB) is read. If all three of the FIFO's receive holding registers are full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exists, the contents of the FIFO are not affected, but the character previously in the shift register is lost and the overrun-error status bit will be set upon receipt of the start bit of the new overrunning character. To support flow control, a receiver can automatically negate and reassert the ready-toreceive (RTR) output (alternate function of parallel outputs OP0 and OP1). The RTS and RTR functions both use OP0 (channel A) and/or OP1 (channel B). Both functions should not be enabled for the same channel at the same time. If programmed to operate in this mode, the ready-to-receive output will automatically be negated by the receiver when a valid start bit is received and the FIFO stack is full. When a FIFO position becomes available, the ready-to-receive output will be reasserted automatically by the receiver. Connecting the ready-to-receive output to the clear-to-send (CTS) input of a transmitting device, prevents overrun errors in the receiver. The RTR output must be manually asserted the first time. Thereafter, the receiver will control the RTR output. If the FIFO stack contains characters and the receiver is then disabled, the characters in the stack can still be read but no additional characters can be received until the receiver is again enabled. If the receiver is disabled while receiving a character, or while there is a character in the shift register waiting for a FIFO opening, these characters are lost. If the receiver is reset, the FIFO stack and all of the receiver status bits, the corresponding output ports, and the interrupt request are reset. No additional characters can be received until the receiver is again enabled.
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3.3 LOOPING MODES
Besides the normal operation mode in which the receiver and transmitter operate independently, each DUART channel can be configured to operate in various looping modes that are useful for local and remote system diagnostic functions. These modes are described in the following paragraphs with additional information available in Section 4 Programming and Register Descriptions.
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3.3.1 Automatic-Echo Mode
In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-to-receiver communication continues normally but the CPU-to-transmitter link is disabled.
3.3.2 Local-Loopback Mode
In this mode, the transmitter output is internally connected to the receiver input. The external TxD pin is held in the mark (high) state in this mode. This mode is useful for testing the operation of a local DUART channel. By sending data to the transmitter and checking that the data assembled by the receiver is the same data that was sent, proper channel operation can be assured. In this mode the CPU-to-transmitter and CPU-to-receiver communications continue normally.
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3.3.3 Remote-Loopback Mode
In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-to-receiver and CPU-to-transmitter links are disabled. This mode is useful in testing the receiver and transmitter operation of a remote channel. This mode requires the remote channel receiver to be enabled.
3.4 MULTIDROP MODE
Customers can program the channel to operate in a wake-up mode for multidrop applications. This mode is selected by setting bits three and four in mode register one (MR1). In this mode of operation, a master station's channel, connected to several slave stations (a maximum of 256 unique slave stations), transmits an address character followed by a block of data characters targeted for one or more of the slave stations. In this mode, the channel receivers within the slave stations are disabled, but they continuously monitor the data stream sent out from the master station. When the slave station's channel receivers detect any address character in the data stream, each receiver notifies its respective CPU by setting receiver ready (RxRDY) and generating an interrupt, if programmed to do so. Each slave station CPU then compares the received address to its station address and enables its receiver if it wants to receive the subsequent data from the master station. Slave stations that are not addressed continue monitoring the data stream for the next address character. An address character flags the end of one block of data and the start of another. After receiving a block of data, the slave station's CPU may disable the channel receiver and re-initiate the process. A transmitted character from the master station consists of a start bit, the programmed number of data bits, an address/data (A/D) bit flag, and the programmed number of stop bits. The address/data bit identifies to the slave station's channel whether the character should be interpreted as an address character or a data character. The character is interpreted as an address character if the A/D bit is set to a one or interpreted as a data character if it is set to a zero. The polarity of the transmitted address/data bit is selected by programming bit two in mode register one (MR1) to a one for an address character and to a zero for data characters. Customers should program the mode register prior to loading the corresponding data or address characters into the transmit buffer (TBA or TBB).
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Operation
In the multidrop mode, the receiver continuously monitors the received data stream regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the receiver ready status bit and loads the character into the FIFO receive holding register stack provided the received address/data bit is a one (address tag). The received character is discarded if the received address/data bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU by way of the receive holding register stack during read operations. In either case, the data bits are loaded into the data portion of the FIFO stack while the address/data bit is loaded into the status portion of the FIFO stack normally used for parity error (status register bit five). Framing error, overrun error, and breakdetection operate normally regardless of whether the receiver is enabled or disabled.
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The address/data bit takes the place of the parity bit and parity is neither calculated nor checked for characters in this mode. Nevertheless, messages in this mode can still contain error detection and correction information. One way to provide error detection (if 8-bit characters are not required) would be to use software to calculate parity and append it to 5-, 6-, or 7-bit characters. Another way to provide error detection for the entire message would be to use cyclic redundancy checks, or Hamming codes similar to those used in synchronous protocols, perform the check in software, and append the check character(s) to the end of the message.
3.5 COUNTER/TIMER
The 16-bit counter/timer (C/T) can operate in a counter mode or a timer mode. In either mode, customers can program the C/T input (clock source) to come from several sources and program the C/T output to appear on output port pin OP3. The value (preload value) stored in the concatenation of the C/T upper register (CTUR) and the C/T lower register (CTLR) can be from 000116 through FFFF16 and can be changed at any time. In counter mode, the CPU can start and stop the C/T. This mode allows the C/T to function as a system stopwatch, a real-time single interrupt generator, or a device watchdog. In timer mode, the C/T runs continuously; the CPU cannot start or stop it. Instead, the CPU only resets the C/T interrupt. This mode allows the C/T to be used as a programmable clock source for channels A and B, or periodic interrupt generator. At power-up and after reset, the C/T operates in timer mode.
3.5.1 Counter Mode
In counter mode, the C/T counts down from the preload value using the programmed counter clock source. The counter clock source can be the channel A transmitter clock, the channel B transmitter clock, the external clock on the X1 pin divided by sixteen, or an external clock on the input port pin IP2. The CPU can start and stop the counter, and can read the count value (CUR:CLR) if the counter is stopped. When a read at the start counter command address is performed, the counter is initialized to the preload value and begins a countdown sequence. When the counter counts from 000116 to 000016 (terminal count), the C/T-ready bit in the interrupt status register (ISR[3]) is set.
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Customers can program the counter to generate an interrupt request for this condition on the IRQ output or output pin OP3. After 000016 the counter counts to FFFF16, and continues counting down from there. If the CPU changes the preload value, the counter will not recognize the new value until it receives the next start counter command (and is reinitialized). When a read at the stop counter command address is performed, the counter stops the countdown sequence and clears ISR[3]. The count value should only be read while the counter is stopped because only one of the count registers (either CUR or CLR) can be read at a time. If the counter is running, a decrement of CLR that requires a borrow from the CUR could take place between the two reads.
3.5.2 Timer Mode
In timer mode, the C/T generates a square-wave output derived from the programmed timer input (clock source). The timer clock source can be the external clock on the X1 input pin divided by one or sixteen, or it can be an external input on input port pin IP2 divided by one or sixteen. The square wave generated by the timer has a period of 2x (preload value) x (period of clock source), is available as a clock source for both communications channels and can be programmed to appear on output pin OP3. The timer runs continuously; the CPU cannot stop it. Because the timer cannot be stopped, the count value (CUR:CLR) should not be read. When a read at the start counter command address is performed, the timer terminates the current countdown sequence, sets its output to 1 (appears uninverted at OP3), is initialized to the preload value, and begins a new countdown sequence. When the counter counts from 000116 (terminal count), it inverts its output, is re-initialized to the preload value and repeats the countdown sequence. After reaching terminal count a second time, the timer sets the C/T-ready bit in the interrupt status register (ISR[3]), inverts its output, is re-initialized again, and begins a new countdown sequence. Customers can program the timer to generate an interrupt request for this condition (every second countdown cycle) on the IRQ output. If the CPU changes the preload value, the timer will not recognize the new value until either (a) it reaches the next terminal count and is reinitialized automatically, or (b) it is forced to re-initialize by a start command. When a read at the stop counter command address is performed, the timer clears ISR[3] but does not stop. Because in timer mode the C/T runs continuously, it should be completely configured (preload value loaded and start counter command issued) before programming the timer output to appear on OP3.
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SECTION 4 PROGRAMMING AND REGISTER DESCRIPTIONS
4.1 PROGRAMMING DESCRIPTIONS
Customers program the DUART by writing control words into the appropriate registers. The status registers provide operational feedback that the CPU reads. Table 4-1 describes the DUART register address and address-triggered commands. Figure 4-1 illustrates a block diagram of the DUART from a programming perspective and details the register configuration for each block. Table 4-1 and Figure 4-1 should be referred to during the discussion of the programming features of the DUART.
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DTACK R/W CS RESET RS4-RS1
INTERNAL CONTROL LOGIC
TIMING LOGIC X1 X2
CSRA CHANNEL A CLOCK SELECT REG CSRB CHANNEL B CLOCK SELECT REG ACR W W
AUXILIARY CONTROL REG (4 BITS) W COUNTER/TIMER LOWER REGISTER (LEAST SIGNIF 8 BITS) W*
COUNTER/TIMER UPPER REGISTER (MOST SIGNIF 8 BITS) W*
* Current Count in Counter Mode may be Read
INTERNAL DATA BUS
PROCESSOR INTERFACE
EXTERNAL INTERFACE CHANNEL A
CRA MR1A MR2A SRA TBA THRA COMMAND REGISTER MODE REGISTER 1 MODE REGISTER 2 STATUS REGISTER TRANSMIT HOLDING REG TRANSMIT SHIFT REG RHRA RECEIVE HOLDING REG (3) RHRA (2) RHRA (1) RECEIVE SHIFT REGISTER R W R/W R/W R W
4
D7-D0
DATA BUS BUFFER
TxDA
RBA
FIFO RxDA
CHANNEL B
CRB MR1B MR2B SRB TBB THRB COMMAND REGISTER MODE REGISTER 1 MODE REGISTER 2 STATUS REGISTER TRANSMIT HOLDING REG TRANSMIT SHIFT REGISTER RHRB R W R/W RBB W RECEIVE HOLDING REG (3) RHRB (2) RHRB (1) RECEIVE SHIFT REGISTER R W R/W R/W R W
TxDB FIFO RxDB
INTERRUPT CONTROL LOGIC
IRQ IACK
IMR
INTERRUPT MASK REG
ISR INTERRUPT STATUS REG ACR * AUX CONTROL REG (4 BITS) Same ACR as in Input Port * IVR INTERRUPT VECTOR REG
INPUT PORT
IPCR INPUT PORT CHANGE REG R W R
IP5-IP0
AUX CONTROL REG (4 BITS) ACR * * Same ACR as in Interrupt Control Logic ACR INPUT PORT (6 BITS)
VCC GND
OPCR OPR
OUTPUT PORT
OUTPUT PORT CONFIG REG OUTPUT PORT REG (8 BITS) W W
OP7-OP0
Figure 4-1. Programming Block Diagram
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Table 4-1. Register Addressing and Address-Triggered Commands
RS4 RS3 RS2 RS1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 NOTES: 1. 2. Reading From This Address Is Prohibited In The MC68681. Address Triggered Commands. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mode Register A Status Register A Clock-Select Register A Receiver Buffer A Input Port Change Register Interrupt Status Register Counter Mode: Current MSB of Counter Counter Mode: Current LSB of Counter Mode Register B Status Register B Clock-Select Register B 2 Receiver Buffer B Interrupt-Vector Register Input Port Start-Counter Command 3 Stop-Counter Command 3
1
READ (R/W = 1) (MR1A, MR2A) Mode Register A
WRITE (R/W = 0) (MR1A, MR2A) (CSRA) (CRA) (TBA) (ACR) (IMR) (CTUR) (CTLR) (MR1B, MR2B) (CSRB) (CRB) (TBB) (IVR) (OPCR)
(SRA) Clock-Select Register A (CSRA) Command Register A (RBA) Transmitter Buffer A (IPCR) Auxiliary Control Register (ISR) Interrupt Mask Register (CUR) Counter/Timer Upper Register (CLR) Counter/ Timer Lower Register (MR1B, MR2B) Mode Register B (SRB) Clock-Select Register B (CSRB) Command Register B (RBB) Transmitter Buffer B (IVR) Interrupt-Vector Register (IP) Output Port Configuration Register Output Port Register (OPR) Bit Set Command 3 Bit Reset Command 3
4
Table 4-2 summarizes the various input port pin functions.
Table 4-2. Programming of Input Port Functions
INPUT PORT PIN FUNCTION IP5 General Purpose Change-of-State Detector External Counter 1X Clock Input External Timer 16X Clock Input External Timer 1X Clock Input Default* No IP4 Default* No IP3 Default* Yes IP2 Default* Yes ACR[6:4] = 000 ACR[6:4] = 100 ACR[6:4] = 101 IP1 Default* Yes IP0 Default* Yes
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Table 4-2. Programming of Input Port Functions (Continued)
INPUT PORT PIN FUNCTION IP5 RxCA 16X RxCA 1X TxCA 16X TxCA 1X RxCB 16X RxCB 1X IP4 CSRA[7:4] = 1110 CSRA[7:4] = 1111 CSRA[3:0] = 1110 CSRA[3:0] = 1111 CSRB[7:4] = 1110 CSRB[7:4] = 1111 CSAB[3:0] = 1110 CSRB[3:0] = 1111 MR2A[4] = 1 MR2B[4] = 1 NOTE: IP3 IP2 IP1 IP0
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TxCB 16X TxCB 1X TxCTSA TxCTSB
The pin is in this mode unless program med to operate in another mode.
Table 4-3 summarizes the various output port pin functions.
Table 4-3. Programming of Output Port Functions
OUTPUT PORT PIN FUNCTION OP7 General Purpose CTRDY Timer Output TxCB 1X RxCB TxCA 16X TxCA 1X RxCA 1X OPCR[7] = 0 OP6 OPCR[6] = 0 OP5 61PCR[5] = 0 OP4 OPCR[4] = 0 OP3 OP2 OP1 OP0 OPCR[3:2] = 00 OPCR[1:0] = 00 MR1B[7] = 0 MR1B[7] = 0 MR2B[5] = 0 MR2A[5] = 0 OPCR[3:2] = 01, ACR[6] = 0* OPCR[3:2] = 01, ACR[6] = 1* OPCR[3:2] = 10 OPCR[3:2] = 11 OPCR[1:0] = 01 OPCR[1:0] = 10 OPCR[1:0] = 11
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Table 4-3. Programming of Output Port Functions (Continued)
OUTPUT PORT PIN FUNCTION OP7 TxRDYA TxRDYB RxRDYA RxRDYB FFULLA FFULLB RxRTRA TxRTSA RxRTRB TxRTSB NOTE: MR1B[7] = 1 MR2B[5] = 1 OPCR[5] = 1 MR1B[6] = 1* MR1A[7] = 1 MR2A[5] = 1 OPCR[5] = 1 MR1B[6] = 0* OPCR[4] = 1, MR1A[6] = 1* OPCR[7] = 1* OPCR[4] = 1 MR1A[6] = 0* OP6 OPCR[6] = 1* OP5 OP4 OP3 OP2 OP1 OP0
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The pin requires a pull-up resistor.
Table 4-4 summarizes the various clock sources that can be selected for the counter/ timer.
Table 4-4. Selection of Clock Sources for the Counter/Timer
ACR[6] = 0 (COUNTER MODE) COUNTER MODE CLOCK SOURCES Input Port Pin IP2 Channel A 1X Transmitter Clock TxCA Channel B 1X Transmitter Clock TxCB Crystal/Clock X1 Divided by 16 ACR[5:4] = 00 01 10 11 ACR[6] = 1 (TIMER MODE) TIMER MODE CLOCK SOURCES Input Port Pin IP2 Input Port Pin IP2 Divided by 16 Crystal/Clock X1 Crystal/Clock X1 Divided by 16 ACR[5:4] = 00 01 10 11
Customers should use caution if the contents of a register are changed during receiver/ transmitter operation as certain changes can produce undesired results. For example, changing the number of bits per character while the transmitter is active can transmit an incorrect character. The contents of the clock-select register (CSR) and bit 7 of the auxiliary control register (ACR[7]) should only be changed after the receiver(s) and transmitter(s) have been issued software Rx and Tx reset commands. Most bits of the mode registers should not be changed during receiver/transmitter operation, except that in multidrop parity mode, the address/data parity type bit can be changed at any time.
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Similarly, certain changes to the auxiliary control register (ACR bits six through four) should only be made while the counter/timer (C/T) is not used (i.e., stopped if in counter mode, output and/or interrupt masked in timer mode). Channel A mode registers MR1A and MR2A are accessed via an auxiliary pointer. The pointer is set to mode register one (MR1A) by RESET or by issuing a "reset pointer" command via the channel A command register. Any read or write of the mode register switches the pointer to mode register two (MR2A). All subsequent accesses will address MR2A unless the pointer is reset to MR1A as described above. The channel B mode registers MR1B and MR2B are accessed by an identical pointer independent of the channel A pointer. Mode, command, clock-select, and status registers are duplicated for each channel to allow independent operation and control (except that both channels are restricted to baud rates that are in the same set).
4.2 REGISTER BIT FORMATS
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Channel A/B Mode Register 1 (MR1A/MR1B) 7 6 5 4 3 ERROR RX RTR RX IRQ PARITY MODE MODE
2 PARITY TYPE
1
0
BITS PER CHARACTER
Rx RTR--Control 0 = Disabled 1 = Enabled Rx IRQ = Select 0 = RxRDY 1 = FFULL Error Mode 0 = Character 1 = Block Parity Mode (Bits 4 and 3) 0 0 = With Parity 0 1 = Force Parity 1 0 = No Parity 1 1 = Multidrop Mode Parity Type With Parity 0 = Even 1 = Odd
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Force Parity 0 = Low 1 = High Multidrop Mode 0 = Data 1 = Address Bits-per-Character (Bits 1 and 0) 00=5 01=6 10=7 11=8
Channel A Mode Register 2 (MR2A/MR2B) 7 6 5 4 CHANNEL MODE TX RTS CTS
3 2 STOP BIT LENGTH
1 UNUSED
0
4
Channel Mode (Bits 7 and 6) 0 0 = Normal 0 1 = Automatic Echo 1 0 = Local Loopback 1 1 = Remote Loopback Tx RTS--Control 0 = Disabled 1 = Enabled CTS--Enable Transmitter 0 = Disabled 1 = Enabled Stop Bit Length (Bits 3, 2) 0 0 = 1 Stop Bit 0 1 = 1 Stop Bit 1 0 = 1.5 Stop Bits (Async mode); 2 Stop Bits (Sync mode) 1 1 = 2 Stop Bits
Clock-Select Register A/B (CSRA/CSRB) 7 6 5 4 RECEIVER-CLOCK SELECT
3
2 1 TRANSMITTER CLOCK SELECT
0
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Receiver (Bits 7-4) And Transmitter (Bits 3-0) Clock Selec
t
BIT 7 0 0 0 0 0 0 0 0 1
BIT 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BIT 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BIT 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SET 1 50 110 134.5 200 300 600 1200 1050 2400 4800 7200 9600 38.4K Timer IPn-16X IPn-1X
SET 2 75 110 134.5 150 300 600 1200 2000 2400 4800 1800 9600 19.2K Timer IPn-16X IPn-1X
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1 1 1 1 1 1 1
All clock selects are 16X (async) except code 1111. Ch A Tx uses IP3 Ch A Rx uses IP4 Ch B Tx uses IP5 Ch B Rx uses IP2
Channel A/B Command Register (CRA/CRB) 7 6 5 4 X MISCELLANEOUS COMMANDS
3 2 TRANSMITTER COMMANDS
1
0
RECEIVER COMMANDS
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X--Not Used, may be set to either 0 or 1 Miscellaneous Commands (Bits 6, 5, 4) 0 0 0 = No Command 0 0 1 = Reset MR Pointer to MR1 0 1 0 = Reset Receiver 0 1 1 = Reset Transmitter 1 0 0 = Reset Error Status 1 0 1 = Reset Channel's Break-Change Interrupt 1 1 0 = Start Break 1 1 1 = Stop Break Transmitter Commands (Bits 3 and 2) 0 0 = No Action, Stays in Present Mode 0 1 = Transmitter Enabled 1 0 = Transmitter Disabled 1 1 = Don't Use, Indeterminate Receiver Commands (Bits 1 and 0) 0 0 = No Action, Stays in Present Mode 0 1 = Receiver Enabled 1 0 = Receiver Disabled 1 1 = Don't Use, Indeterminate
Channel A/B Status Register (SRA/SRB) 7* 6* 5* 4 RECEIVED FRAMING PARITY OVERRUN BREAK ERROR ERROR ERROR
4
3 TXEMT
2 TXRDY
1 FFULL
0 RXRDY
These status bits are appended to the corresponding data character in the receive FIFO and are valid only when the RxRDY bit is set. A read of the status register provides these bits (seven through five) from the top of the FIFO together with bits four through zero. These bits are cleared by a reset error status command. In character mode, they are discarded when the corresponding data character is read from the FIFO.
All Bits 0 = No 1 = Yes
Output Port Configuration Register (OPCR) 7 6 5 4 OP7 OP6 OP5 OP4
3 OP3
2
1 OP2
0
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OP7 0 = OPR Bit 7 1 = TxRDYB OP6 0 = OPR Bit 6 1 = TxRDYA OP5 0 = OPR Bit 5 1 = RxRDYB/FFULLB OP4 0 = OPR Bit 4 1 = RxRDYA/FFULLA
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OP3 (Bits 3 and 2) 0 0 = OPR Bit 2 0 1 = C/T Output1 1 0 = TxCB (1X) 1 1 = TxCB (1X) OP2 (Bits 1 and 0) 0 0 = OPR Bit 2 0 1 = TxCA (16X) 1 0 = TxCA (1X) 1 1 = RxCA (1X) Alternate functions of OP1 and OP0 (TxRTS, RxRTR) are controlled by the mode registers, not the OPCR. MR1A[7] and MR2A[5] control OP0; MR1B[7] and MR2B[5] control OP1.
Output Port Register (OPR) 7 6 5 OPR7 OPR6 OPR5
4 OPR4
3 OPR3
2 OPR2
1 OPR1
0 OPR0
All bits, unless programmed for alternate function 0 = Pin driven high 1 = Pin driven low
1.
If OP3 is to be used for the timer output, customers should program the counter/timer for timer mode (ACR[6] = 1), initialize the counter/timer preload registers (CTUR and CTLR), and the start counter command issued before setting OPCR[3:2] = 01.
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Auxiliary Control Register (ACR) 7 BRG SET SELECT 6 5 4 3 2 1 0
COUNTER/TIMER
IP0 IP1 IP2 IP3 CHANGE CHANGE CHANGE CHANGE VISIBLE IN VISIBLE IN VISIBLE IN VISIBLE IN ISR ISR ISR ISR
BRG Set Select. Should only be changed after both channels have been reset and are disabled. 0 = Set 1 1 = Set 2 Counter/Timer--Mode and Clock Source. Should only be altered while the C/T is not in use (i.e., stopped if in counter mode, output and/or interrupt masked if in timer mode). Mode Clock Source 000 Counter External (IP2) 0 0 1Counter TxCA--1X Clock of Channel A Transmitter 0 1 0Counter TxCB--1X Clock of Channel B Transmitter 0 1 1Counter Crystal or External Clock (X1/Clk) Divided by 16 1 0 0Timer External (IP2) 1 0 1Timer External (IP2) Divided by 16* 110 Timer Crystal or External Clock (X1/Clk) 1 1 1Timer Crystal or External Clock (X1/Clk) Divided by 16 IP Change-Of-State Visible in ISR (Bits 3, 2, 1, 0) 0 = Disabled 1 = Enabled
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Input Port Change Register (IPCR) 7 6 5 4 3 2 IP2 LEVEL 1 IP1 LEVEL 0 IP0 LEVEL
IP3 DELTA IP2 DELTA IP1 DELTA IP0 DELTA IP3 LEVEL
IP Delta (Change-of-state) (Bits 7,6,5,4). 0 = No 1 = Yes IP Level (Bits 3,2,1,0). 0 = Low 1 = High
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Interrupt Status Register (ISR) 7 6 5 RXRDYB/ FFULLB 4 TXRDYB 3 COUNTER/ TIMER READY 2 DELTA BREAK A 1 RXRDYA/ FFULLA 0 TXRDYA
INPUT PORT DELTA CHANGE BREAK B
All Bits 0 = This interrupt source is not active 1 = This interrupt source is active
Interrupt Mask Register (IMR) 7 6 5 RXRDYB/ FFULLB 4 TXRDYB 3 COUNTER/ TIMER READY 2 DELTA BREAK A 1 RXRDYA/ FFULLA 0 TXRDYA
4
INPUT PORT DELTA CHANGE BREAK B
All Bits 0 = Mask this interrupt source 1 = Allow this interrupt source to assert IRQ
Counter/Timer Upper Register (CTUR) 7 6 5 4 C/T[15] C/T[14] C/T[13] C/T[12]
3 C/T[11]
2 C/T[10]
1 C/T[9]
0 C/T[8]
Counter/Timer Lower Register (CTLR) 7 6 5 4 C/T[7] C/T[6] C/T[5] C/T[4]
3 C/T[3]
2 C/T[2]
1 C/T[1]
0 C/T[0]
Interrupt Vector Register (IVR) 7 IVR[7] 6 IVR[6] 5 IVR[5] 4 IVR[4] 3 IVR[3] 2 IVR[2] 1 IVR[1] 0 IVR[0]
Input Port 7 6 5 4 3 2 1 0 * IP5 IP4 IP3 IP2 IP1 IP0 * Bit seven has no external pin. Upon reading the input port, bit seven will always be read as a one Bit six has no external pin. Upon reading the input port, bit six will reflect the current logic level of IACK
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4.3 REGISTER DESCRIPTION
The following paragraphs provide a detailed description of each register and its function.
4.3.1 Channel A Mode Register 1 (MR1A)
The channel A mode register one (MR1A) is accessed when the channel A mode register pointer points to MR1. The pointer is set to MR1 by RESET or by a "set pointer" command applied via command register A. After reading or writing MR1A, the pointer will point to channel A mode register two (MR2A). 4.3.1.1 CHANNEL A RECEIVER READY-TO-RECIEVE CONTROL -- MR1A[7]. This bit allows the parallel output OP0 to be used as a ready-to-receive indicator (RTRA), controlled by the channel A receiver. OP0 must first be asserted by setting OPR[0]. MR1A[7] = 1 causes RTRA to be negated on receipt of a valid start bit if the channel A FIFO is full. RTRA will be reasserted when an empty FIFO position is available. This feature can be used for flow control to prevent overrun in the receiver by using the RTRA output signal to control the clear-to-send CTS input of the transmitting device. 4.3.1.2 CHANNEL A RECEIVER-INTERRUPT SELECT - MR1A[6]. This bit selects either the channel A receiver-ready status (RxRDY) or the channel A FIFO full status (FFULL) to be used for CPU interrupts. It also causes the selected bit to be output on the parallel output OP4 if OP4 is programmed as an interrupt output via the output port configuration register (OPCR). 4.3.1.3 CHANNEL A ERROR MODE SELECT - MR1A[5]. This bit selects the operating mode of the three FIFO status bits (framing error (FE), parity error (PE), and received break (RB)) for channel A. In the "character" mode, status provided in the status register is given on a character-by-character basis and applies only to the character at the top of the FIFO. In the "block" mode, the status provided in the status register for these bits is the accumulation (logical OR) of the status for all characters coming to the top of the FIFO since the last reset error status command for channel A was issued. 4.3.1.4 CHANNEL A PARITY MODE SELECT - MR1A[4:3]. If "with parity" or "force parity" is selected, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. MR1A[4:3] = 11 selects channel A to operate in the multidrop mode as described in Section 3.4 Multidrop Mode. 4.3.1.5 CHANNEL A PARITY TYPE SELECT - MR1A[2]. This bit selects the parity type (odd or even) in "with parity" mode; the polarity of the forced parity bit in "force parity" mode; or the state of the address/data tag bit in "multidrop" mode. It has no effect in "no parity" mode. 4.3.1.6 CHANNEL A BITS-PER-CHARACTER SELECT - MR1A[1:0]. This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits.
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4.3.2 Channel A Mode Register 2 (MR2A)
The channel A mode register two (MR2A) is accessed when the channel A mode register pointer points to MR2, which occurs after any access to channel A mode register one (MR1A). Accesses to MR2A do not change the pointer. 4.3.2.1 CHANNEL A MODE SELECT - MR2A[7:6]. Each channel of the DUART can operate in one of four modes: normal, automatic echo, local loopback, or remote loopback. MR2A[7:6] = 00 is the normal mode, with the transmitter and receiver operating independently. MR2A[7:6] = 01 places the channel in the automatic echo mode, which automatically retransmits the received data. The following conditions are true while in the automatic-echo mode: * Received data is reclocked and retransmitted on the channel A transmitter serial-data output. * The receive clock is used for the transmitter. * The receiver must be enabled, but the transmitter need not be enabled.
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* The channel A transmitter ready and transmitter empty status bits are inactive. * The received parity is checked, but is not recalculated for transmission; i.e., the transmitted parity bit is as received. * Character framing is checked but the stop bits are retransmitted as received. * A received break is echoed as received until the next valid start bit is detected. * CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. Two diagnostic modes can also be configured. MR2A[7:6] = 10 selects the first of these, the local- loopback mode. In this mode * The transmitter output is internally connected to the receiver input. * The transmit clock is used for the receiver. * The channel A transmitter serial-data output is held high. * The channel A receiver serial-data input is ignored. * The transmitter must be enabled, but the receiver need not be enabled. * CPU-to-transmitter and receiver communications continue normally.
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The second diagnostic mode is the remote-loopback mode, selected by MR2A(7:6] = 11. * Received data is reclocked and retransmitted on the channel A transmitter serial-data output. * The receive clock is used for the transmitter. * Received data cannot be read by the local CPU and the error status conditions are inactive. * The received parity is not checked and is not recalculated for transmission; i.e., the transmitted parity bit is as received. * The receiver must be enabled. * Character framing is not checked, and the stop bits are retransmitted as received. * A received break is echoed as received until the next valid start bit is detected. Switching between modes should be done only while the channel is disabled. 4.3.2.2 CHANNEL A TRANSMITTER REQUEST-TO-SEND CONTROL - MR2A[5]. This bit controls the negation of the channel A transmitter request-to-send (RTSA) parallel output (OP0) by the transmitter. OP0 must be asserted before each message by setting OPR[0]. MR2A[5] = 1 causes OPR[0] to be cleared automatically one bit time after the characters in the channel A transmit shift register and the transmit holding register, if any, are completely transmitted, including the programmed number of stop bits, and the transmitter is disabled. This feature can indicate the end of a message as follows: 1. Program the DUART for the automatic-reset mode: MR2A[5] = 1. 2. Enable the transmitter. 3. Assert channel A transmitter request-to-send control: OPR[0] = 1. 4. Send the message. 5. Disable the transmitter. The transmitter can be disabled any time after the last character has been loaded into the transmit holding register. Note, however, that disabling the transmitter forces the TxRDY and TxEMT status bits in the status register to be inactive. If it is necessary to know when the last character transmission is complete, do not disable the transmitter until transmission is complete, as signalled by TxEMT. In the MC68681, if the transmitter was disabled after transmission was complete, RTS would not be negated. This is not true in the MC68HC681. 6. The last character will be transmitted and OPR[0] will be cleared one bit time after the last stop bit, causing the channel A transmitter request-to-send control to be negated. Note that in this mode, a character in the holding register at the time of the disable command is not held back. In the MC68681, if (1) clear-to-send control was enabled (see Paragraph 4.3.2.3), (2) the transmitter was disabled with a character in the holding register, and (3) CTS was negated at the time of the disable command, the character in the holding register would not be sent, even if CTS was later asserted. This is not true in the MC68HC681.)
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4.3.2.3 CHANNEL A CLEAR-TO-SEND CONTROL - MR2A[4]. If this bit is zero, channel A clear-to-send control (CTSA) has no effect on the transmitter. If this bit is a one, the transmitter checks the state of CTSA (IP0) each time it is ready to send a character. If IP0 is asserted (low), the character is transmitted. If it is negated (high), the channel A transmitter serial-data output remains in the marking state and the transmission is delayed until CTSA goes low. Changes of CTSA while a character is being transmitted do not affect the transmission of that character. 4.3.2.4 CHANNEL A STOP BIT LENGTH SELECT - MR2A[3:2]. This field programs the number of stop bits appended to transmitted characters. One, one-and-a-half (async mode only), or two stop bits can be programmed for any character length. In all cases, the receiver checks only for a "mark" condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled).
4.3.3 Channel B Mode Register 1 (MR1B)
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The channel B mode register one (MR1 B) is accessed when the channel B mode register pointer points to MR1. The pointer is set to MR1 by RESET or by a "set pointer" command applied via command register B. After reading or writing MR1B, the pointer will point to channel B mode register two (MR2B). The bit definitions for this register are identical to the bit definitions for MR1A, except that all control actions apply to the channel B receiver and transmitter and their corresponding inputs and outputs.
4.3.4 Channel B Mode Register 2 (MR2B)
The channel B mode register two (MR2B) is accessed when the channel B mode register pointer points to MR2, which occurs after any access to channel B mode register one (MR1 B). Accesses to MR2B do not change the pointer. The bit definitions for this register are identical to the bit definitions for MR2A, except that all control actions apply to the channel B receiver and transmitter and their corresponding inputs and outputs.
4.3.5 Channel A Clock-Select Register (CSRA)
In the paragraphs below, ACR[7] controls the set of available baud rates. 4.3.5.1 CHANNEL A RECEIVER CLOCK SELECT - CSRA[7:4]. This field selects the baud-rate clock for the channel A receiver from the set of available baud rates. The receiver clock is always 16 times the baud rate given in the table except for CSRA[7:4] = 1111, when an external 1X clock is used. When CSRA[7:5] = 111, the receiver uses the external clock connected to parallel input IP4. 4.3.5.2 CHANNEL A TRANSMITTER CLOCK SELECT - CSRA[3:0]. This field selects the baud rate clock for the channel A transmitter from the set of available baud rates. The transmitter clock is always 16 times the baud rate given in the table except for CSRA[3:0] = 1111, when an external 1X clock is used. When CSRA[3:1] = 111, the external clock connected to parallel input IP3 is used by the transmitter.
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4.3.6 Channel B Clock-Select Register (CSRB)
The bit definitions for this register are identical to those for CSRA, except that all control actions apply to the channel B receiver and transmitter and their corresponding inputs and outputs. 4.3.6.1 CHANNEL B RECEIVER CLOCK SELECT - CSRB[7:4]. When CSRB[7:5] = 111, the receiver uses the external clock connected to parallel input IP2. 4.3.6.2 CHANNEL B TRANSMITTER CLOCK SELECT - CSRB[3:0]. When CSRB[3:1] = 111, the transmitter uses the external clock connected to parallel input IP5.
4.3.7 Channel A Command Register (CRA)
The command(s) to be issued are encoded in the data value written to the command register address. Multiple commands can be specified in a single write to CRA provided the commands are nonconflicting; e.g., the "enable transmitter" and "reset transmitter" commands cannot be specified in a single command word. 4.3.7.1 CRA[7]. This bit is not used and may be set to either zero or one. 4.3.7.2 CHANNEL A MISCELLANEOUS COMMANDS - CRA[6:4]. The encoded value of this field specifies a single command as follows:
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CRA[6:4] 000 001 010 No command.
COMMAND
Reset Mode Register Pointer. This command causes the channel A mode register pointer to point to mode register one. Reset Receiver. This command resets the channel A receiver. The receiver is immediately disabled, the RxRDY and FFULL bits in the SRA are cleared, and the RxFIFO pointer is reinitialized. All other registers are unaltered. This command should be used in lieu of the receiver disable command whenever the receiver configuration is to be changed, as it places the receiver in a guaranteed known state. Reset Transmitter. This command resets the channel A transmitter. The transmitter is immediately disabled and the TxRDY and TxEMT bits in the SRA are cleared. All other registers are unaltered. This command should be used in lieu of the transmitter disable command whenever the transmitter configuration is to be changed, as it places the receiver in a guaranteed known state. Reset Error Status. This command clears the channel A received break (RB), parity error (PE), framing error (FE), and overrun error (OE) flags in the status register (SRA[7:4]). This command is used in the character mode to clear OE status (RB, PE, and FE bits will also be cleared) and is used in the block mode to clear all error status flags after a block of data has been received.
011
100
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CRA[6:4] 101 110
COMMAND Reset Channel A Break Change Interrupt. This command causes the channel A break detect change bit in the interrupt status register (ISR[2]) to be cleared to zero. Start Break. This command forces the channel A transmitter serial-data output (TxDA) low (spacing). If the transmitter is empty, the start of the break condition will be delayed up to two bit times. If the transmitter is active, the break begins when transmission of the character is completed. If a character is in the transmit holding register, the start of the break will be delayed until that character Stop Break. The channel A transmitter serial-data output (TxDA) line will go high (marking) within two bit times. TxDA will remain high for one bit time before the next character, if any, is transmitted.
111
NOTE: The error bits must actually be cleared before reading the last character of the block, unless it can be guaranteed that
no more characters are in the FIFO after the last character of the current block.
4.3.7.3 CHANNEL A TRANSMITTER COMMANDS - CRA[3:2]. The encoded value of this field specifies a single command for the transmitter as follows:
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CRA[3:2] 00 01 10
COMMAND No action is taken. The transmitter stays in its present mode. If the transmitter was enabled it remains enabled, if disabled it remains disabled. Enable Transmitter. This command enables operation of the channel A transmitter. Disable Transmitter. This command terminates transmitter operation and resets the transmitter-ready and transmitter-empty status bits. However, if a character is being transmitted when the transmitter is disabled, the transmission of the character is completed before assuming the inactive state. Illegal command; do not use.
11
4.3.7.4 CHANNEL A RECEIVER COMMANDS - CRA[1:0]. The encoded value of this field specifies a single command for the receiver as follows:
CRA[1:0] 00 01 10
COMMAND No action is taken. The receiver stays in its present mode. If the receiver was enabled it remains enabled, if disabled it remains disabled. Enable Receiver. This command enables operation of the channel A receiver. If the DUART is not in the multidrop mode, this command also forces the receiver into the search-for-start-bit state. Disable Receiver. This command terminates operation of the receiver immediately - a character being received, or waiting in the shift register for an opening in the receive FIFO, will be lost. The command has no effect on the receiver status bits or any other control register. If the DUART has been programmed to operate in the local loopback or multidrop mode, the receiver operates even if it is disabled. Refer to Section 3 Operation for further information. Illegal command; do not use.
11
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4.3.8 Channel B Command Register (CRB)
The bit definitions for this register are identical to those for CRA, except that all control actions apply to the channel B receiver and transmitter and their corresponding inputs and outputs.
4.3.9 Channel A Status Register (SRA)
4.3.9.1 CHANNEL A RECEIVED BREAK - SRA[7]. This bit indicates an all-zero character of the programmed length has been received without a stop bit. This bit is valid only when the RxRDY bit is set (SRA[0] = 1). Only a single FIFO position is occupied when a break is received; additional entries to the FIFO are inhibited until the channel A receiver serial data input line returns to the marking state. The break-detect circuitry can detect a break that starts in the middle of a received character; however, the break condition must persist completely through the end of the current character and the next character time to be recognized. (The MC68681 incorrectly signalled a break if the data bits and stop bit were 0, but the parity bit was 1. This is not true in the MC68HC681.) 4.3.9.2 CHANNEL A FRAMING ERROR - SRA[6]. This bit (when set) indicates that a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. This bit is valid only when the RxRDY bit is set (SRA[0] = 1). Framing error and break are exclusive: At least one data bit and/or the parity bit must have been a 1 to signal a framing error. After a framing error, the receiver does not wait for the line to return to the marking state (high); if the line remains low for 1/2 a bit time after the stop bit sample (that is, the nominal end of the first stop bit), the receiver treats it as the beginning of a new start bit. 4.3.9.3 CHANNEL A PARITY ERROR - SRA[5]. This bit becomes set when the "with parity" or "force parity" mode is programmed by mode register one and the corresponding character in the FIFO is received with incorrect parity. In the multidrop mode, the parity error bit position stores the received address/data bit. This bit is valid only when the RxRDY bit is set (SRA[0] = 1). 4.3.9.4 CHANNEL A OVERRUN ERROR - SRA[4]. This bit (when set) indicates one or more characters in the received data stream have been lost. It becomes set on receipt of a valid start bit when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error, and framing error status, if any) is lost. A reset error status command clears this bit. 4.3.9.5 CHANNEL A TRANSMITTER EMPTY - SRA[3]. This bit will be set when the channel A transmitter underruns; i.e., both the transmit holding register and the transmit shift register are empty. It is set after transmission of the last stop bit of a character if no character is in the transmit holding register awaiting transmission. It is cleared when the CPU loads the transmit holding register or when the transmitter is disabled.
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4.3.9.6 CHANNEL A TRANSMITTER READY - SRA[2]. This bit (when set) indicates that the transmit holding register is empty and ready to be loaded with a character. Transmitter ready is set when the character is transferred to the transmit shift register. This bit is cleared when the the CPU loads the transmit holding register, or when the transmitter is disabled. 4.3.9.7 CHANNEL A FIFO FULL - SRA[1]. This bit is set when a character is transferred from the receive shift register to the receiver FIFO and the transfer fills the FIFO; i.e., all three FIFO holding register positions are occupied. It is cleared when the CPU reads the receiver buffer, unless a fourth character is in the receive shift register waiting for an empty FIFO slot. 4.3.9.8 CHANNEL A RECEIVER READY - SRA[0]. This bit indicates that one or more character(s) has been received and is waiting in the FIFO for the CPU to read it. It is set when the first character is transferred from the receive shift register to the empty FIFO, and cleared when the CPU reads the receiver buffer, if there are no more characters in the FIFO after the read.
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4.3.10 Channel B Status Register (SRB)
The bit definitions for this register are identical to those for SRA, except the status applies to the channel B receiver and transmitter and their corresponding inputs and outputs.
4.3.11 Output Port Configuration Register (OPCR)
This register individually configures each bit of the 8-bit parallel output port for generalpurpose use or an auxiliary function serving the communication channels. 4.3.11.1 OP7 OUTPUT SELECT - OPCR[7]. This bit programs the parallel output OP7 to provide either the complement of OPR[7] or the channel B transmitter interrupt output, which is the complement of ISR[4] (not masked by the interrupt mask register). When configured for the channel B transmitter interrupt, OP7 acts as an open-collector output. 4.3.11.2 OP6 OUTPUT SELECT - OPCR[6]. This bit programs the parallel output OP6 to provide either the complement of OPR[6] or the channel A transmitter interrupt output, which is the complement of ISR[0] (not masked by the interrupt mask register). When configured for the channel A transmitter interrupt, OP6 acts as an open-collector output. 4.3.11.3 OP5 OUTPUT SELECT - OPCR[5]. This bit programs the parallel output OP5 to provide either the complement of OPR[5] or the channel B receiver interrupt output, which is the complement of ISR[5] (not masked by the interrupt mask register). When configured for the channel B receiver interrupt, OP5 acts as an open-collector output. 4.3.11.4 OP4 OUTPUT SELECT - OPCR[4]. This bit programs the parallel output OP4 to provide either the complement of OPR[4] or the channel A receiver interrupt output, which is the complement of ISR[1] (not masked by the interrupt-mask register). When configured for the channel A receiver interrupt, OP4 acts as an open-collector output.
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4.3.11.5 OP3 OUTPUT SELECT - OPCR[3:2]. This field programs the parallel output OP3 to provide one of the following:
OPCR[3:2] 00 01 Complement of OPR[3].
OP3 FUNCTION
Counter/timer output, open-collector. In counter mode (ACR[6]=0), OP3 is the complement of ISR[3] (not masked by the interrupt mask register). In timer mode (ACR[6]=1), this output is a square wave at the programmed frequency. Because the timer cannot be stopped, OPCR[3:2] should be cleared until the timer has been programmed for the desired operation. 1X bit-rate clock of the channel B transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free-running 1X clock is output. 1X bit-rate clock of the channel B receiver, which is the clock that samples the received data. If data is not being received, a free-running 1X clock is output.
10 11
4.3.11.6 OP2 OUTPUT SELECT - OPCR[1:0]. This field programs the parallel output OP2 to provide one of the following:
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OPCR[1:0] 00 01 10 Complement of OPR[2].
OP2 FUNCTION
16X bit-rate clock of the channel A transmitter. This is the clock selected by CSRA[3:0] and will be a 1X clock if CSRA[3:0] = 1 1 1 1. 1X bit-rate clock of the channel A transmitter, which is the clock that shifts the transmitted data. A free running 1X clock is always output in this mode. If data is not being transmitted, a free-running 1X clock is output. 1X bit-rate clock of the channel A receiver, which is the clock that samples the received data. A free running 1X clock is always output in this mode. If data is not being received, a free-running 1X clock is output.
11
4.3.12 Output Port Register - OPR[7:0]
These bits contain the complement of the logic levels output at the output port pins (OP7OPO). Customers can set these register bits by performing a write to the bit set command address, with data specifying the bits to be set (one equals set, zero equals no change). Customers can clear these register bits by performing a write to the bit reset command address, with data specifying the bits to be cleared (one equals reset, zero equals no change).
4.3.13 Auxiliary Control Register (ACR)
4.3.13.1 BAUD-RATE GENERATOR SET SELECT - ACR[7]. This bit selects the set of baud-rate generator outputs available for use by the channel A and B receivers and transmitters. Baud-rate generator characteristics are given in Table 4-5.
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Table 4-5. Baud-Rate Generator Characteristics Crystal or Clock = 3.6864 MHz
NOMINAL RATE (BAUD) 50 75 100 134.5 150 200 300 600 1050 ACTUAL 16X CLOCK (KHZ) 0.8 1.2 1.759 2.153 2.4 3.2 48 9.6 16.756 ERROR (PERCENT) 0 0 -0.069 0.059 0 0 0 0 -0.260 NOMINAL RATE (BAUD) 1200 1800 2000 2400 4800 7200 9600 19.2k 38.4k ACTUAL 16X CLOCK (KHZ) 19.2 28.8 32.056 38.4 76.8 1115.2 153.6 307.2 614.4 ERROR (PERCENT) 0 0 0.175 0 0 0 0 0 0
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4.3.13.2 COUNTER/TIMER MODE AND CLOCK SOURCE SELECT -- ACR[6:4]. This field selects the operating mode of the counter/timer and its clock source as shown in Table 4-4. 4.3.13.3 IP3, IP2, IP1, AND IP0 CHANGE-OF-STATE INTERRUPT ENABLE -- ACR[3:0]. These four bits are logically ANDed with IPCR[7:4], and the results are ORed to produce ISR[7].
4.3.14 Input Port Change Register (IPCR)
4.3.14.1 IP3, IP2, IP1, AND IP0 CHANGE OF STATE - IPCR[7:4]. These bits are set at 25-50 microseconds, which occurs at their respective input pins. They are cleared when the CPU reads the input port change register. 4.3.14.2 IP3, IP2, IP1, AND IP0 CURRENT STATE -- IPCR[3:0]. These bits provide the current state of their respective inputs. The information reflects the state of the input pins at the time the input port change register is read.
4.3.15 Interrupt Status Register (ISR)
This register provides the status of all potential interrupt sources. The contents of this register are logically ANDed with the contents of the interrupt mask register, and the results are NORed to produce the IRQ output. All active interrupt sources are visible by reading the ISR, regardless of the contents of the interrupt mask register. Reading the ISR has no effect on any interrupt source; each active interrupt source must be cleared in a source-specific fashion to clear the ISR. All interrupt sources are cleared when the DUART is reset.
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4.3.15.1 INPUT PORT CHANGE STATUS - ISR[7]. This bit is a one when a change of state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been enabled to cause an interrupt by the programming of ACR[3:0]. This bit is cleared when the CPU reads the input port change register. 4.3.15.2 CHANNEL B CHANGE IN BREAK -- ISR[6]. This bit (when set) indicates that the channel B receiver has detected the beginning or the end of a break condition. It is reset when the CPU issues a channel B reset break change interrupt command. 4.3.15.3 CHANNEL B RECEIVER READY OR FIFO FULL -- ISR[5]. The function of this bit is programmed by MR1B[6]. If programmed as receiver ready, it is a copy of the channel B status register RxRDY bit (SRB[0]). If programmed as FIFO full, it is a copy of the channel B status register FFULL bit (SRB[1]). 4.3.15.4 CHANNEL B TRANSMITTER READY -- ISR[4]. This bit is a duplicate of the channel B status register transmitter ready bit (SRB[2]). 4.3.15.5 COUNTER/TIMER READY -- ISR[3]. In counter mode, this bit is set when the counter reaches terminal count. In timer mode, this bit is set each time the timer output switches from low to high (every other time that the C/T reaches terminal count). (In both the MC68681 and the MC68HC681, a timer-start command forces the timer output high. In the MC68681, if this caused a low-to-high transition of the timer output, this bit would be set. This is not true in the MC68HC681.) In either mode, the bit is cleared by a C/T stop command. 4.3.15.6 CHANNEL A CHANGE IN BREAK -- ISR[2]. This bit is the channel A equivalent of ISR[6]. 4.3.15.7 CHANNEL A RECEIVER READY OR FIFO FULL -- ISR[1]. This bit is the channel A equivalent of ISR[5]. 4.3.15.8 CHANNEL A TRANSMITTER READY -- ISR[0]. This bit is the channel A equivalent of ISR[4].
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4.3.16 Interrupt Mask Register (IMR)
This register selects which bits in the interrupt status register can cause an interrupt output. If a bit in the interrupt status register is a one and the corresponding bit in this register is also a one, the IRQ output will be asserted. If the corresponding bit in this register is a zero, the state of the bit in the interrupt status register has no effect on the IRQ output. Note that the interrupt mask register does not mask the programmable interrupt outputs OP7 through OP3 or the value read from the interrupt status register.
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4.3.17 Count Registers (CUR and CLR)
The count upper register (CUR) and count lower register (CLR) hold the most-significant byte and the least-significant byte, respectively, of the current counter value. These registers should only be read when the C/T is in counter mode and the counter is stopped. See Section 3.5 Counter/Timer for additional information.
4.3.18 Counter/Timer Preload Registers (CTUR and CTLR)
The C/T upper register (CTUR) and C/T lower register (CTLR) hold the most-significant byte and eight least-significant bytes, respectively, of the preload value to be used by the C/T in either counter or timer mode. The minimum value that can be loaded into the concatenation of CTUR with CTLR is 000116. Note that CTUR and CTLR are write-only registers and cannot be read by the CPU.
4.3.19 Interrupt Vector Register (IVR)
This register contains the interrupt vector. When the DUART responds to a valid interrupt acknowledge (IACK) cycle, the contents of this register are placed on the data bus. At reset, this register will contain 0F16, which is the M68000 exception vector assignment for uninitialized interrupt vectors.
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SECTION 5 ELECTRICAL SPECIFICATIONS
5.1 ABSOLUTE MAXIMUM RATINGS
RATING Supply Voltage Input Voltage Operating Temperature Range Storage Temperature SYMBOL VCC Vin TA Tstg VALUE -0.5 to + 6.0 -0.5 to + 6.0 0 to + 70 -65 to + 150 UNIT V V C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
5.2 THERMAL CHARACTERISTICS
CHARACTERISTIC Thermal Resistance (Still Air) Plastic, Type FN Type P NOTE: Estimate SYMBOL JA 45 50 VALUE SYMBOL JC 22 25 VALUE RATING C/W
5
5.3 POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in C can be obtained from: TJ = TA + (PD*JA) Where: TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + PI/O PINT = ICC x VCC, Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output Pins - User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Solving equations 1 and 2 for K gives: K = PD*(TA + 273C) + JA*PD2 (3) (2) (1)
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Where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the outside ambient (CA). These terms are related by the equation: JA = JC + CA (4)
JC is device-related and cannot be influenced by customers. However, CA is customerdependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal convention. Thus, good thermal management on the part of the customer can significantly reduce CA so that JA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature. Values for thermal resistance presented in this data sheet, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, "Thermal Resistance Measurement Method for MC68XX Microcomponent Devices", and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. Customer-derived values for thermal resistance may differ.
5.4 DC ELECTRICAL CHARACTERISTICS
5
TA = 0C to 70C, VCC = 5.0 V 5% All voltage measurements are referenced to ground (GND).
CHARACTERISTIC Input High Voltage, Except X1 Input High Voltage, X1 Input Low Voltage Output High Voltage, Except Open-Collector Outputs (IOH = -) Output Low Voltage (IOL = ) Input Leakage Current (Vin = 0 to VCC) Data Bus Hi-Z Leakage Current (Vout = 0 to VCC) Open-Collector Output Leakage Current (Vout = 0 to VCC) Power Supply Current Capacitance (Vin = 5 V, TA = 25C, f = 1 MHz) X1 Low Input Current Vin = 0, X2 Floated X1 High lnput Current Vin = VCC, X2 Floated SYMBOL VIH VIH VIL VOH VOL IIL ILL IOC ICC Cin IX1L IX1H -- -10 -- MIN 2.0 4.0 -- 2.4 -- -5 -5 -5 MAX -- -- 0.8 -- 0.6 5 5 5 25 15 -- 10 UNIT V V V V V A A A mA pF mA mA
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5.5 AC ELECTRICAL CHARACTERISTICS
TA = 0C to 70C, VCC = 5.0 V 5% All voltage measurements are referenced to ground (GND). For testing, all input signals except X1 swing between 0.4 V and 2.4 V with a maximum transition time of 20 ns. For X1, the swing is between 0.4 V and 4.4 V. All time measurements are referenced at input and output voltages of 0.8 V and 2.0 V as appropriate. Test conditions for non-interrupt outputs: CL= pF, RL= to VCC. Test conditions for interrupt outputs: CL= pF, RL= to VCC
5.5.1 Clock Timing
CHARACTERISTIC X1 Frequency* X1 High or Low Time Counter/Timer Clock Frequency Counter/Timer Clock High or Low Time Receiver Clock Frequency (RxC) 16X Clock 1X Clock Receive Clock (RxC) High or Low Time Transmitter Clock Frequency (TxC) 16X Clock 1X Clock Transmit Clock (TxC) High or Low Clock Rise Time Clock Fall Time SYMBOL fCLK tCLK fCTC tCTC fRx tRx fTx tTx tr tf MIN 0 100 0 25 0 0 100 0 0 100 -- -- MAX 4.0 -- 16.0 -- 4.0 1.0 -- 4.0 1.0 -- 20 20 UNIT MHz ns MHz ns MHz ns MHz ns ns ns
5
NOTE: * For the baud-rate generator to generate the standard baud rates shown in Section 4.2 Register Bit Formats, the X1 frequency should be set to 3.6864 MHz or a 3.6864 MHz crystal should be connected across pins X1 and X2.
X1 C/T CLK RxC TxC tr
t CLK t CTC t Rx t Tx
t CLK t CTC t Rx t Tx
tf
Figure 5-1. Clock Timing
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5.5.2 RESET Timing
CHARACTERISTIC RESET Pulse Width* NOTE: * The MC68HC681 does not require a clock for correct reset SYMBOL tRES MIN 1.0 MAX -- UNIT s
RESET t RES
Figure 5-2. RESET Timing
5.5.3 Read and Write Bus Cycle Timing
CHARACTERISTIC CS Setup Time to X1 High 1 RS1-RS4 Setup Time to CS Asserted R/W Setup Time to CS Asserted CS Pulse Width Asserted 2 Data Valid from CS Asserted DTACK Asserted from X1 High SYMBOL tCSC tRSS tRWS tCSWL tDD tDCR tCSD tRSH tRWH tDH tDF tDAH tDAT tCSWH tDSCS tDCW tDH MIN 90 10 10 205 -- -- 0 0 0 0 -- -- -- 90 100 -- 0 MAX -- -- -- -- 175 125 -- -- -- -- 100 100 125 -- -- 125 -- UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5
CS Negated from DTACK Asserted 2 RS1-RS4 Hold Time from CS Negated R/W Hold Time from CS Negated Data Hold Time from CS Negated Data Bus Floating from CS Negated DTACK Negated from CS Negated DTACK Hi-Z from CS Negated CS Pulse Width Negated Data Setup Time to CS Negated 3 DTACK Asserted from X1 High Data Hold Time from CS Negated NOTES: 1.
This specification is only to ensure DTACK is asserted with respect to the rising edge of X1 as shown in Figure 5-3 and Figure 54, not to guarantee operation of the part. If the setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later. This specification is only to ensure that DTACK will be asserted. If CS is negated before DTACK is asserted, DTACK may not be asserted. During write cycles, the MC68681 latched data on either the assertion edge of DTACK or the negation edge of CS, whichever occurred first. This is not true in the MC68HC681: the MC68HC681 always latches write data on the negation edge of CS .
2. 3.
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Electrical Specifications
5.5.4 Interrupt Bus Cycle Timing
CHARACTERISTIC IACK Setup Time to X1 High 1 R/W Setup Time to IACK Asserted 2 IACK Pulse Width Asserted Data Valid from IACK Asserted DTACK Asserted from X1 High IACK Negated from DTACK Asserted 3 R/W Hold Time from IACK Negated Data Hold Time from IACK Negated Data Bus Floating from IACK Negated DTACK Negated from IACK Negated DTACK Hi-Z from IACK Negated NOTES: 1. This specification is only to ensure DTACK is asserted with respect to the rising edge of X1 as shown in Figure 5-3 and Figure 54, not to guarantee operation of the part. If the setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later. During IACK cycles, the MC68681 ignored R/W; this is not true in the MC68HC681: R/W must be high on IACK cycles. The MC68HC681 ignores IACK if R/W is low. This specification is only to ensure that DTACK will be asserted. If IACK is negated before DTACK is asserted, DTACK may not be asserted. SYMBOL tCSC tRWS tIAWL tDD tDCR tCSD tRWH tDH tDF tDAH tDAT MIN 90 10 205 -- -- 0 0 0 -- -- -- MAX -- -- -- 175 125 -- -- -- 100 100 125 UNIT ns ns ns ns ns ns ns ns ns ns ns
2. 3.
5
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MC68HC681 USER'S MANUAL
5-5
Electrical Specifications
t CSC X1 t RSS RS4-RS1 t RWS R/W t CSWL CS t CSWH t RWH t RSH
t DF t DD D0-D7 tCSD DTACK t DAH t DC t DAT t DH
Figure 5-3. Read Cycle Bus Timing
5
t CSC X1 t RSS RS4-RS1 t RWS R/W t CSWL CS t DSCS D0-D7 t DS DTACK t CSD t DAH t DCW t DAT t DH t CSWH t RWH t RSH
Figure 5-4. Write Cycle Bus Timing
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Electrical Specifications
t CSC X1/CLK
IRQ t IAWL IACK * t DD D0-D7 t DH t DF
tCSD DTACK tDAH t DCR t DAT
* CS and IACK should not be asserted simultaneously. Figure 5-5. Interrupt Cycle Bus Timing
5.5.5 Port Timing
CHARACTERISTIC Port Input Setup Time to CS Asserted Port 1nput Hold Time from CS Negated Port Output Valid from CS Negated SYMBOL tPS tPH tPD MIN 10 0 -- MAX -- -- 400 UNIT ns ns ns
5
CS t PS IP0-IP5 t PH
CS t PD OP7-OP0 OLD DATA NEW DATA
Figure 5-6. Port Timing
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5-7
Electrical Specifications
5.5.6 Interrupt Reset Timing
CHARACTERISTIC IRQ Negated or OP3-OP7 High (When Used as Interrupts) From CS Negated: Reset Receiver Command (RxRDY/FFULL interrupt) Read RB (RxRDY/FFULL interrupt) Reset Transmitter Command (TxRDY interrupt) Write TB (TxRDY Interrupt) Reset Break Change Interrupt Command (Delta Break Interrupt) Stop Counter/Timer Command (Counter/Timer Interrupt) Read IPCR (Input Port Change Interrupt) Write IMR (Clear a Mask Bit) SYMBOL tIR -- -- -- -- -- -- -- -- -- 300 300 300 300 300 300 300 300 300 ns ns ns ns ns ns ns ns ns MIN MAX UNIT
CS (READ OR WRITE CYCLE)
tIR
INTERRUPT OUTPUT
*
* IRQ or OP3-OP7 when used as interrupt outputs.
Figure 5-7. Interrupt Reset Timing
5
5.5.7 Transmitter Timing
CHARACTERISTIC TxD Output Valid from TxC Low TxC Low to TxD Output Valid SYMBOL tTxD tTCS MIN -- -- MAX 350 150 UNIT ns ns
1 BIT TIME (1 OR 16 CLOCKS)
TxC (INPUT) t TxD TxD t TCS TxC (1X OUTPUT)
Figure 5-8. Transmitter Timing
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Electrical Specifications
5.5.8 Receiver Timing
CHARACTERISTIC RxD Data Setup Time to RxC High RxD Data Hold Time from RxC High SYMBOL tRxS tRxH MIN 240 200 MAX -- -- UNIT ns ns
RxC (1X INPUT) t RxS RxD t RxH
Figure 5-9. Receiver Timing
5
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5-9
Electrical Specifications
5.5.9 Transmitter and Receiver Operation
C1 IN TRANSMISSION
TxDx
C1
C2
C3
BREAK
C4
C6
TRANSMITTER ENABLED
TxRDY (SR2)
CS W C1 CTS 1 (IP0) W C2
W C3
W START BREAK
W C4
W STOP BREAK
W C5 NOT TRANSMITTED
W C6
RTS 2 (OP0)
MANUALLY ASSERTED BY BIT- SET COMMAND
MANUALLY ASSERTED
5
NOTES: 1. TIMING SHOWN FOR MR2(4) = 1 2. TIMING SHOWN FOR MR2(5) = 1 3. C N = TRANSMIT CHARACTER 4. W = WRITE
Figure 5-10. Transmitter Operation
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Electrical Specifications
RxD
C1
C2
C3
C4
C5
C6
C7
C8
C6, C7, C8 ARE LOST RECEIVER ENABLED
RxRDY (SR0)
FFULL (SR1)
CS R R STATUS DATA C1 OVERRUN (SR4) C5 LOST RR SD C2 RRRR S D S D STATUS (S) DATA (D) C4 C3
RTS 1 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. C N = Received Character
RESET BY COMMAND
5
Figure 5-11. Receiver Operation
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MC68HC681 USER'S MANUAL
5-11
SECTION 6 MECHANICAL DATA AND ORDERING INFORMATION
6.1 PIN ASSIGNMENTS
RS3 IP1 RS2 IP3 RS1 NC VCC IP4 IP5 IACK IP2 6 RS4 IP0 R/W DTACK RxDB NC TxDB OP1 OP3 OP5 OP7 7 1 40 39 CS RESET X2 X1/CLK RxDA NC TxDA OP0 OP2 OP4 OP6 MC68HC681FN 17 18 28 29
6.2 ORDERING INFORMATION
D1 D3 D5 D7 GND NC IRQ D6 D4 D2 D0
6
PACKAGE TYPE Plastic PLCC FN Suffix FREQUENCY (MHZ) 4.0 TEMPERATURE 0 C to 70 C ORDER NUMBER MC68HC681FN
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6-1
Mechanical Data and Ordering Information
6.3 PACKAGE DIMENSIONS
0.007(0.180) M T U L-M N
N
Y
BRK
D
B
S
S S
0.007(0.180) M T
L-M
N
S
L
M
Z
V
44 1
W
D
X VIEW DD
G1 0.010 (0.25)
S
T
L-M
S
N
S
A R Z
0.007(0.180) M T 0.007(0.180) M T
L-M L-M
S S
N N
S S
H
0.007(0.180) M T
L-M
S
N
S
J C G G1 0.010 (0.25)
S
E 0.004 (0.10) T SEATING
PLANE
K1 K F 0.007(0.180) M T VIEW S L-M
S
T
L-M
S
N
S
VIEW S
N
S
6
NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION T O BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION T O BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2 10 0.610 0.630 0.040 ---
MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2 10 15.50 16.00 1.02 ---
NOTES: 1. 2. 3. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
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Mechanical Data and Ordering Information
6.4 PIN ASSIGNMENT -- 40 PIN DUAL-IN-LINE PLASTIC PACKAGE
RS1 IP3 RS2 IP1 RS3 RS4 IP0 W R RxDB TxDB OP1 OP3 OP5 OP7 D1 D3 D5 D7 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC68HC681P 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC IP4 IP5 IP6 IP2 CS RESET X2 X1/CLK RxDA TxDA OP0 OP2 OP4 OP6 D0 D2 D4 D6 IRQ
6.5 ORDERING INFORMATION
PACKAGE TYPE Plastic P Suffix FREQUENCY (MHZ) 4.0 TEMPERATURE 0 C to 70 C ORDER NUMBER MC68HC681P
6
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Mechanical Data and Ordering Information
6.6 PACKAGE DIMENSIONS -- 40 PIN DUAL-IN-LINE PACKAGE
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
40
21
B
1 20
A N
L C
J H G F D K
SEATING PLANE
M
NOTES: 1. 2. 3. 4. 5. DIMENSION A IS DATUM. POSITIONAL TOLERANCE FOR LEADS: T IS SEATING PLANE. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. DIMENSIONING AND TOLERANCING PER ANSI Y14.5, 1973.
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APPENDIX A MC68HC2681
The MC68HC2681 dual asynchronous receiver/transmitter (DUART) is functionally equivalent to the MC68HC681 with some minor differences. The description of the MC68HC681 applies to the MC68HC2681 except for the areas described below.
A.1 INTRODUCTION
Unlike the MC68HC681, which has an M68000 bus interface, the MC68HC2681 has a general-purpose interface that can be used with both synchronous and asynchronous microprocessors. The device has a multipurpose 7-bit input port and a multipurpose 8-bit output port. These ports can be used as general-purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. Figure A-1 is a block diagram for the MC68HC2681.
A.1.1 Interrupt Control Logic
The internal operation of interrupt events and registers is identical to the MC68HC681; however, the MH68HC2681 does not have an IACK pin, and therefore does not support Interrupt Acknowledge bus cycles. The IVR can be written and read but cannot be used to vector the CPU to an interrupt service routine.
A.1.2 Input Port
The MC68HC2681 input port pins and associated registers are identical to those of the MC68HC681, with the exception of an extra pin (IP6) and the Channel B Receiver Clock Select programming (CSRB(7-4)).
A.2 SIGNAL DESCRIPTION
Table A-1, like that for the MC68HC681 found in Section 2 Signal Descriptions, provides a quick reference in determining a signal's pin number, its use as an input or output, whether it is active high or low, and the section containing more information about its operation. The signal description given for the MC68HC681 applies to the MC68HC2681 except for the areas described in this appendix.
A
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A-1
MC68HC2681
.
R W C RESET RS1-RS4
INTERNAL CONTROL LOGIC
TIMING LOGIC X1/CLK X2 CRYSTAL OSCILLATOR BAUD RATE GENERATOR CLOCK SELECTORS INTERNAL DATA BUS COUNTER/ TIMER
PROCESSOR INTERFACE DATA BUS BUFFER D0-D7
EXTERNAL INTERFACE CHANNEL A TWO- CHARACTER Tx BUFFER FOUR-CHARACTER Rx BUFFER TxDA RxDA
INTERRUPT CONTROL LOGIC IRQ
CHANNEL B TWO-CHARACTER Tx BUFFER FOUR-CHARACTER Rx BUFFER TxDB
RxDB
V CC GND
INPUT PORT
CHANGE-OFSTATE DETECTORS (4)
IP0-IP6
A
OUTPUT PORT
OP0-OP7
Figure A-1. MC68HC2681 Block Diagram
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MC68HC2681
Table A-1. MC68HC2681 Signal Summary
PIN NO. SIGNAL NAME Power Supply ( + 5 V) Ground Crystal Input or External Clock Crystal Output Reset Chip Select Write Strobe Read Strobe Register-Select Bus Bit 4 Register-Select Bus Bit 3 Register-Select Bus Bit 2 Register-Select Bus Bit 1 Bidirectional-Data Bus Bit 7 Bidirectional-Data Bus Bit 6 Bidirectional-Data Bus Bit 5 Bidirectional-Data Bus Bit 4 Bidirectional-Data Bus Bit 3 Bidirectional-Data Bus Bit 2 Bidirectionai-Data Bus Bit 1 Bidirectional-Data Bus Bit 0 Interrupt Request Channel A Transmitter Serial Data Channel A Receiver Serial Data Channel B Transmitter Serial Data Channel B Receiver Serial Data Parallel Input 6 Parallel Input 5 Parallel Input 4 Parallel Input 3 Parallel Input 2 Parallel Input 1 Parallel Input 0 Parallel Output 7 Parallel Output 6 Parallel Output 5 Parallel Output 4 Parallel Output 3 Parallel Output 2 Parallel Output 1 Parallel Output 0 NOTES: 1. 2. Requires a pull-up resistor. May require a pull-up resistor, depending on its programmed function. MNEMONIC P PKG. FN PKG. VCC GND X1 X2 RESET CS W R RS4 RS3 RS2 RS1 D7 D6 D5 D4 D3 D2 D1 D0 IRQ TxDA RxDA TxDB RxDB IP6 IP5 IP4 IP3 IP2 IP1 IP0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 40 20 32 33 34 35 8 9 6 5 3 1 19 22 18 23 17 24 16 25 21 30 31 11 10 37 38 39 2 36 4 7 15 26 14 27 13 28 12 29 44 22 36 37 38 39 9 10 7 6 4 2 21 25 20 26 19 27 18 28 24 33 35 13 11 41 42 43 3 40 5 8 17 29 16 30 15 31 14 32 In In In Out In In In In In/Out In In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out 1 Out In Out In In In In In In In In Out 2 Out 2 Out 2 Out 2 Out 2 Out Out Out High Low Low Low High High High High High High High High High High High High Low -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN/OUT ACTIVE STATE High Low REFER TO PARA. NO. 2.1 2.1 2.2 2.3 A.2.1 A.2.2 A.2.3 A.2.4 2.8 2.8 2.8 2.8 2.9 2.9 2.9 2.9 2.9 2.9 2.9 2.9 2.10 2.12 2.13 2.14 2.15 A.2.5 2.16.1 2.16.2 2.16.3 A.2.6 2.16.5 2.16.6 2.17.1 2.17.2 2.17.3 2.17.4 2.17.5 2.17.6 2.17.7 2.17.8
A
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A-3
MC68HC2681
A.2.3 Reset (RESET)
Operation is identical to the MC68HC681 RESET, except it is active high.
A.2.4 Chip-Select (CS)
This active low signal is used in conjunction with R and W to enable data transfers between the CPU and DUART. If CS and R are both low, a read cycle occurs; if CS and W are both low, a write cycle occurs. CS by itself does not cause any data transfer.
A.2.5 Write Strobe (W)
This active low signal is used in conjunction with CS to enable data to be written to a DUART register. The write occurs at the rising edge of W or CS, whichever occurs first. W by itself does not cause any data transfer.
A.2.6 Read Strobe (R)
This active low signal is used in conjunction with CS to enable data to be read from a DUART register. The read occurs at the falling edge of R or CS, whichever occurs last. W by itself does not cause any data transfer.
A.2.7 Parallel Input 6 (IP6)
This signal can be used as a general-purpose input or a channel B receiver external clock input (RxCB). When the receiver uses the external clock , the received data is sampled on the rising edge of the clock.
A.2.8 Parallel Input 2 (IP2)
This signal can be used as a general-purpose input or a counter/timer (C/T) external clock input. This signal cannot be used as a channel B receiver external clock; IP6 provides that functionality in the MC68HC2681.
A.3 PROGRAMMING AND REGISTER DESCRIPTION
Table A-2 describes the register addresses and address-triggered commands for the MC68HC2681. The detailed description of each register and its function, given for the MC68HC681 in Section 4 Programming and Register Descriptions, applies to the MC68HC2681.
A
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MC68HC2681
Table A-2. MC68HC2681 Register Addressing and Address-Triggered Commands
RS4 RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NOTES: 1. 2. 3. Reading from this address is prohibited in the MC2681. This register serves no useful function in the MC2681 or MC68HC2681. Address-triggered command. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mode Register A Status Register A Clock Select Register A Receiver Buffer A Input Port Change Register Interrupt Status Register Counter Mode: Current MSB of Counter Counter Mode: Current LSB of Counter Mode Register B Status Register B Clock Select Register B 2 Receiver Buffer B Interrupt Vector Registe Input Port Start Counter Command 3 Stop Counter Command 3
2 1
READ (MR1A, MR2A) Mode Register A (SRA) Clock Select Register A (CSRA) Command Register A (RBA) Transmit Buffer A
WRITE (MR1A, MR2A) (CSRA) (CRA) (TBA) (ACR) (IMR) (CTUR) (CTLR) (MR1B, MR2B) (CSRB) (CRB) (TBB) (IVR) (OPCR) Bit Set Command Bit Reset Command
(IPCR) Auxiliary Control Register (ISR) Interrupt Mask Register (CUR) Counter/ Timer Upper Register (CLR) Counter/Timer Lower Register (MR1B, MR2B) Mode Register B (SRB) Clock Select Register B (CSRB) Command Register B (RBB) Transmit Buffer B (IVR) Interrupt Vector Register 2
(IP) Output Port Configuration Register Output Port Register (OPR)
A
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MC68HC2681
A.4 ELECTRICAL SPECIFICATIONS A.4.9 Absolute Maximum Ratings
RATING Supply Voltage Input Voltage Operating Temperature Range Storage Temperature SYMBOL VCC Vin TA Tstg VALUE -0.5 to + 6.0 -0.5 to + 6.0 0 to + 70 -65 to + 150 UNIT V V C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage: level (either GND or VCC).
A.4.10 Thermal Characteristics
CHARACTERISTIC Thermal Resistance MC68HC2681 Plastic, Type FN Type P NOTE: Estimate SYMBOL JA 45 50 VALUE SYMBOL JC 22 25 VALUE RATING C/W
A.4.11 DC Electrical Characteristics
TA = 0C to 70C, VCC = 5.0 V 5% All voltage measurements referenced to ground (GND)
CHARACTERISTIC Input High Voltage, Except X1 Input High Voltage, X1 Input Low Voltage Output High Voltage, Except Open-Collector Outputs (IOH = - mA) Output Low Voltage IOL = mA) Input Leakage Current (Vin = 0 to VCC) Data Bus Hi-Z Leakage Current (Vout = 0 to VCC) SYMBOL VIH VIH VIL VOH VOL IIL ILL IOC ICC Cin IX1L IX1H MIN 2.0 4.0 -- 2.4 -- -5 -5 -5 -- -- -10 -- MAX -- -- 0.8 -- 0.4 +5 5 5 25 15 -- 10 UNIT V V V V V mA pF mA mA
A
Open-Collector Output Leakage Current (Vout = 0 to VCC) Power Supply Current Capacitance (Vin = 5 V, TA = 25*C, f = 1 MHz) X1 Low Input Current Vin = 0, X2 Floated X1 High Input Current Vin = VCC, X2 Floated
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A.4.12 AC Electrical Characteristics
TA = 0C to 70C, VCC = 5.0 V 5% All voltage measurements are referenced to ground (GND). For testing, all input signals except X1 swing between 0.4 V and 2.4 V with a maximum transition time of 20 ns. For X1, the swing is between 0.4 V and 4.4 V. All time measurements are referenced at input and output voltages of 0.8 V and 2.0 V as appropriate. Test conditions for non-interrupt outputs: CL = pF, RL = to VCC. Test conditions for interrupt outputs: CL =pF, RL = to VCC. A.4.12.1 CLOCK TIMING
CHARACTERISTIC X1 Frequency * X1 High or Low Time Counter/Timer Clock Frequency Counter Timer Clock High or Low Time Receiver Frequency 16X Clock 1X Clock Receive Clock (RxC) High or Low Time Transmitter Frequency 16X Clock 1X Clock Transmit Clock (TxC) High or Low Time Clock Rise Time Clock Fall Time NOTE:
.
SYMBOL fCLK tCLK fCTC tCTC fRx tRx fTx tTx tr tf
MIN 0 100 0 25 0 0 100 0 0 100
MAX 4.0
UNIT MHz ns
16.0
MHz ns
4.0 1.0 -- 4.0 1.0 -- 20 20
MHz ns MHz ns ns ns
* For the baud-rate generator to generate the standard baud rates shown in Section 4.2 Register Bit Formats, X1 must be 3.6864 MHz
t CLK t CTC t Rx tTx t CLK t CTC t Rx t Tx
X1 C/T CLK RxC TxC tr
tf
Figure A-2. Clock Timing
A
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A-7
MC68HC2681
A.4.12.2 RESET TIMING
CHARACTERISTIC RESET Pulse Width SYMBOL tRES MIN 1.0 MAX -- UNIT
.
RESET
t RES
Figure A-3. RESET Timing A.4.12.3 BUS TIMING
CHARACTERISTIC RS1-RS4 Setup to R+CS, W+CS Asserted RS1-RS4 Hold After R+CS, W+CS Negated Bus Cycle (R+CS, W+CS) Width Inactive Time Between Bus Cycles Read Access Time from R+CS Asserted Read Data Valid After R+CS Negated Data Tri-State After R+CS Negated Write Data Setup to W+CS Negated Write Data Hold After W+CS Negated RS1-RS4 Setup to R+CS, W+CS Asserted RS1-RS4 Hold After R+CS, W+CS Negated
.
SYMBOL tRSS tRSH tRW tRWD tRD tD tDZ tWDS tWDH tRSS tRSH
MIN 10 0 205 200 -- 0 -- 100 10 10 0
MAX -- -- -- -- 175 25 -- -- -- --
UNIT ns ns ns ns ns ns ns ns ns ns ns
RS1RS4 tRSS CS tRW tRSH tRWD
A
R tRD D0-D7 tDZ tD VALID
(READ)
W tWDS D0-D7 (WRITE)
tWDH VALID
Figure A-4. Bus Timing
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A.4.12.4 PORT TIMING
CHARACTERISTIC Port Input Setup Time to R Asserted Port Input Hold Time from R Negated Port Output Valid from W Negated
.
SYMBOL tPS tPH tPD
MIN 10 0 --
MAX -- -- 400
UNIT ns ns ns
R t PS IP0IP6 tPH
W tPD OP0OP7 OLD DATA NEW DATA
Figure A-5. Port Timing A.4.12.5 INTERRUPT RESET TIMING
CHARACTERISTIC IRQ Negated or OP3-OP7 High (When Used as Interrupts) From R or W Negated: Reset Receiver Command (RxRDY/FFULL interrupt) Read RB (RxRDY/FFULL interrupt) Reset Transmitter Command (TxRDY interrupt) Write TB (TxRDY Interrupt) Reset Break Change Interrupt Command (Delta Break Interrupt) Stop Counter/Timer Command (Counter/Timer Interrupt) Read IPCR (Input Port Change Interrupt) Write IMR (Clear a Mask Bit)
.
SYMBOL tIR
MIN -- -- -- -- -- -- -- --
MAX 300 300 300 300 300 300 300 300
UNIT ns ns ns ns ns ns ns ns
R or W and CS t IR
A
IRQ or OP3-OP7
Figure A-6. Interrupt Reset Timing
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MC68HC2681
A.4.12.6 TRANSMITTER TIMING
CHARACTERISTIC TxD Output Valid from TxC Low TxC Low to TxD Output Valid SYMBOL tTxD tTCS MIN MAX 350 150 UNIT ns ns
1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) t TxD TxD t TCS TxC (1XOUTPUT)
Figure A-7. Transmitter Timing A.4.12.7 RECEIVER TIMING
CHARACTERISTIC RxD Data Setup Time to RxC High RxD Data Hold Time from RxC High
.
SYMBOL tRxS tRxH
MIN 240 200
MAX
UNIT ns ns
RxC (1X INPUT) t RxS RxD t RxH
Figure A-8. Receiver Timing
A
A-10
MC68HC681 USER'S MANUAL
MOTOROLA
MC68HC2681
.
TxDx
D1
D2
D3
BREAK
D4
D6
TRANSMITTER ENABLED
TxRDY (SR2)
W
W C1
W C2
W C3
W START BREAK
W C4
W STOP BREAK
W C5 NOT TRANSMITTED
W C6
CTS 1 (IP0)
RTS 2 (OP0) OPR(0)=1 OPR(0)=1
NOTES: 1. TIMING SHOWN FOR MR2(4) = 1 2. TIMING SHOWN FOR MR2(5) = 1 3. C N = TRANSMIT CHARACTER 4. W = WRITE
Figure A-9. Transmitter Operation
A
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MC68HC681 USER'S MANUAL
A-11
MC68HC2681
.
RxD
D1
D2
D3
D4
D5
D6
D7
D8
D6, D7, D8 ARE LOST RECEIVER ENABLED
RxRDY (SR0)
FFULL (SR1) RxRDY, FFULL
R R R STATUS DATA D1 OVERRUN (SR4) D5 LOST RR RRRR STATUS DATA STATUS DATA STATUS DATA D2 D3 D4 RESET BY COMMAND
RTS 1 (OP0)
OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1 2. Timing shown for OPCR(4) = 1 and MR1(6) = 0 3. R = Read 4. C N = Received Character
Figure A-10. Receiver Operation
A
A-12
MC68HC681 USER'S MANUAL
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MC68HC2681
.
MASTER STATION
A/D TxD ADDR 1 1 C0 A/D 0 A/D ADDR 1 2
TRANSMITTER ENABLED
TxRDY (SR2)
W W MR1(4:3) = 11 MR1(2) = 1 W W ADDR1 W MR1(2) = 0 MR1(2) = 1 W W ADDR2
PERIPHERAL STATION
A/D RxD 0 A/D ADDR 1 1 C0 A/D 0 A/D ADDR 1 2 A/D 0
RECEIVER ENABLED
RxRDY
CS W MR1(4-3) = 11 R R W R R R R W
ENABLE
STATUS ENABLE DATA ADDR1
STATUS DATA C0
STATUS DATA ADDR2
Figure A-11. Wake-Up Mode Operation
A
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MC68HC681 USER'S MANUAL
A-13
MC68HC2681
A.5 MECHANICAL DATA AND ORDERING INFORMATION A.5. 1 Pin Assignment -- 44 Pin Plastic Leaded Chip Carrier
RS3 IP1 RS2 IP3 RS1 NC VCC IP4 IP5 IACK IP2 6 RS4 IP0 R/W DTACK RxDB NC TxDB OP1 OP3 OP5 OP7 7 1 40 39 CS RESET X2 X1/CLK RxDA NC TxDA OP0 OP2 OP4 OP6 MC68HC2681FN 17 18 28 29
A.5.2 FN Suffix Ordering Information
PACKAGE TYPE Plastic (FN Suffix) FREQUENCY (MHZ) 4.0 TEMPERATURE 0 C to 70 C ORDER NUMBER MC68HC2681FN
A
A-14
MC68HC681 USER'S MANUAL
D1 D3 D5 D7 GND NC IRQ D6 D4 D2 D0
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MC68HC2681
A.5.3 FN SuffixPackaging Dimensions
.
N
Y
BRK
D
B
0.007(0.180) M T U 0.007(0.180)
L-M
M
S
N
S S
T
L-M
N
S
L
M
Z
V
44 1
W
D
X VIEW DD
G1 0.010 (0.25)
S
T
L-M
S
N
S
A R Z
0.007(0.180) M T 0.007(0.180) M T
L-M L-M
S S
N N
S S
H
0.007(0.180) M T
L-M
S
N
S
J C G G1 0.010 (0.25)
S
E 0.004 (0.10) T SEATING
PLANE
K1 K F 0.007(0.180) M T VIEW S L-M
S
T
L-M
S
N
S
VIEW S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION T O BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION T O BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2 10 0.610 0.630 0.040 ---
MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2 10 15.50 16.00 1.02 ---
A
NOTES: 1. 2. 3. POSITIONAL TOLERANCE OF LEADS (0), SHALL BE WITHIN 0.25mm(0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
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MC68HC681 USER'S MANUAL
A-15
MC68HC2681
A.5.4 Pin Assignment-- 40 PIN Dual-In Line Plastic Package
RS1 IP3 RS2 IP1 RS3 RS4 IP0 W R RxDB TxDB OP1 OP3 OP5 OP7 D1 D3 D5 D7 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC68HC2681P
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC IP4 IP5 IP6 IP2 CS RESET X2 X1/CLK RxDA TxDA OP0 OP2 OP4 OP6 D0 D2 D4 D6 IRQ
A.5.5 P Suffix Ordering Information
PACKAGE TYPE Plastic (P Suffix)
FREQUENCY (MHZ) 4.0
TEMPERATURE 0 C to 70 C
ORDER NUMBER MC68HC2681P
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MC68HC681 USER'S MANUAL
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MC68HC2681
A.5.6 Package Dimensions -- Plastic
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
40
21
B
1 20
A N
L C
J H G F D K
SEATING PLANE
M
A
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MC68HC681 USER'S MANUAL
A-17
INDEX
A
ACR, 4-21 automatic-echo mode, 3-5
F
features MC68HC681, 1-1 formats register bit, 4-6
G B
block diagrams MC68HC2681, A-2 MC68HC681, 1-2 programming, 4-2 GND, 2-2
I
IACK, 2-4 IMR, 4-23 IP0, 2-4 IP0-IP5, 2-4 IP1, 2-5 IP2, 2-5 IP3, 2-5 IP4, 2-5 IP5, 2-5 IPCR, 4-22 IRQ, 2-4 ISR, 4-22 IVR, 4-24
C
clear-to-send, 3-1 clock sources, 4-5 CLR, 4-24 counter mode, 3-6 counter/timer, 3-6 CRA, 4-17 CRB, 4-19 CS, 2-3 CSRA, 4-16 CSRB, 4-17 CTLR, 4-24 CTUR, 4-24 CUR, 4-24
L
local-loopback mode, 3-5 looping modes, 3-4
D
D0-D7, 2-4 descriptions programming, 4-1 register, 4-13 DTACK, 2-4
M
MC68HC2681 electrical specifications, A-6 mechanical data, A-15 ordering information, A-14 Package Dimensions 6-4, A-17 programming and register descriptions, A-4 signal description, A-1 MC68HC2681, A-1 INDE
E
electrical specifications, 5-1
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MC68HC681 USER'S MANUAL
I-1
Index MC68HC681 block diagram, 1-2 introduction, 1-1 operation, 3-1 programming and register descriptions, 4-1 signal descriptions, 2-1 mechanical data, 6-1 mode automatic-echo, 3-5 counter, 3-6 local-loopback, 3-5 looping, 3-4 multidrop, 3-5 remote-loopback, 3-5 timer, 3-7 MR1A, 4-13 MR1B, 4-16 MR2A, 4-14 MR2B, 4-16 multidrop mode, 3-5
P
package dimensions, 6-2 Pin Assignment 6-3 pin functions input port, 4-3 output port, 4-4 programming and register descriptions register bit formats, 4-6 programming descriptions, 4-1 programming, 4-1
R
R/W, 2-3 ready-to-receive, 3-4 receivers, 3-2 register bit formats, 4-6 register descriptions, 4-1, 4-13 remote-loopback mode, 3-5 RESET, 2-3 RS1-RS4, 2-4 RxDA/RxDB, 2-4
O
OP0, 2-5 OP0-OP7, 2-5 OP1, 2-5 OP2, 2-6 OP3, 2-6 OP4, 2-6 OP5, 2-6 OP6, 2-6 OP7, 2-6 OPCR, 4-20 operation counter/timer timer mode, 3-7 counter/timer, 3-6 coutner/timer counter mode, 3-6 looping modes automatic-echo, 3-5 local-loopback, 3-5 remote loopback, 3-5 looping modes, 3-4 multidrop mode, 3-5 receiver, 3-2 transmitter, 3-1 ordering information, 6-1
S
signals, 2-1 specifications electrical, 5-1 SRA, 4-19 SRB, 4-20
T
timer mode, 3-7 transmitters, 3-1 TxDA/TxDB, 2-4
V
VCC, 2-2
DEX
I-2
MC68HC681 USER'S MANUAL
MOTOROLA

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